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    Devices with staggered body contacts
    117.
    发明授权
    Devices with staggered body contacts 有权

    公开(公告)号：US11804491B2

    公开(公告)日：2023-10-31

    申请号：US17872812

    申请日：2022-07-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Anupam Dutta

    IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

    CPC classification number: H01L27/1203 ,  H01L29/41733 ,  H01L29/42384

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.

    Chip module with robust in-package interconnects
    118.
    发明授权
    Chip module with robust in-package interconnects 有权

    公开(公告)号：US11804440B2

    公开(公告)日：2023-10-31

    申请号：US17160447

    申请日：2021-01-28

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Saquib B. Halim ,  Frank G. Kuechenmeister ,  Kashi V Machani ,  Christian Goetze

    IPC: H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/5384 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/14

    Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.

    ELECTROSTATIC DISCHARGE PROTECTION DEVICES INCLUDING A SILICON-CONTROLLED RECTIFIER
    119.
    发明公开
    ELECTROSTATIC DISCHARGE PROTECTION DEVICES INCLUDING A SILICON-CONTROLLED RECTIFIER 审中-公开

    公开(公告)号：US20230343778A1

    公开(公告)日：2023-10-26

    申请号：US17724548

    申请日：2022-04-20

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Prantik Mahajan ,  Ajay ,  Vishal Ganesan ,  Ruchil Jain ,  Souvick Mitra

    IPC: H01L27/02

    CPC classification number: H01L27/0262

    Abstract: Structures for an electrostatic discharge device including a silicon-controlled rectifier and methods of forming a structure for an electrostatic discharge device that includes a silicon-controlled rectifier. The structure includes a first well in a semiconductor substrate, a second well and a third well in the first well, and a fourth well in the first well. The first well has a first conductivity type, and the second well and the third well have the first conductivity type. The fourth well positioned in a lateral direction between the second well and the third well, and the fourth well has a second conductivity type opposite to the first conductivity type. The second well, the third well, and the fourth well are positioned in a vertical direction between the first well and a top surface of the semiconductor substrate.

    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS
    120.
    发明公开
    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS 审中-公开

    公开(公告)号：US20230341888A1

    公开(公告)日：2023-10-26

    申请号：US17726171

    申请日：2022-04-21

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

    IPC: G06F1/10 ,  G06F15/78

    CPC classification number: G06F1/10 ,  G06F15/7839

    Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

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