公开(公告)号：US11505457B2

公开(公告)日：2022-11-22

申请号：US17709932

申请日：2022-03-31

Applicant: XINTEC INC.

Inventor： Yu-Tang Shen ,  Shun-Wen Long ,  Chih-Hung Cho ,  Hsing-Yuan Chu

IPC: B32B43/00 ,  B81C99/00

Abstract: An operation method of a semiconductor removing apparatus includes moving a semiconductor structure to a stage, wherein the semiconductor structure includes a lower substrate, a cap, and a micro electro mechanical system (MEMS) structure between the lower substrate and the cap, and the cap has a diced portion; pulling, by a clamp assembly, a tape of a tape roll from a first side of the stage to a second side of the stage opposite to the first side, such that the tape is attached to the cap of the semiconductor structure; and pulling, by the clamp assembly, the tape of the tape roll from the second side of the stage back to the first side of the stage, such that the diced portion of the cap separates from the semiconductor structure.

公开(公告)号：US20220219970A1

公开(公告)日：2022-07-14

申请号：US17711067

申请日：2022-04-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US11309271B2

公开(公告)日：2022-04-19

申请号：US16941486

申请日：2020-07-28

Applicant: XINTEC INC.

Inventor： Jiun-Yen Lai ,  Chia-Hsiang Chen

IPC: H01L23/00 ,  H01L23/48

Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

公开(公告)号：US20210269303A1

公开(公告)日：2021-09-02

申请号：US17184443

申请日：2021-02-24

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Jiun-Yen LAI ,  Hsing-Lung SHEN ,  Tsang-Yu LIU

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US20210035940A1

公开(公告)日：2021-02-04

申请号：US16941486

申请日：2020-07-28

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Chia-Hsiang CHEN

IPC: H01L23/00 ,  H01L23/48

Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

公开(公告)号：US10833118B2

公开(公告)日：2020-11-10

申请号：US15001065

申请日：2016-01-19

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L27/146

Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

公开(公告)号：US10157875B2

公开(公告)日：2018-12-18

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L27/146 ,  H01L25/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

公开(公告)号：US10109663B2

公开(公告)日：2018-10-23

申请号：US15258594

申请日：2016-09-07

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Tsang-Yu Liu ,  Yi-Ming Chang ,  Hsin Kuan

IPC: H01L27/146

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

公开(公告)号：US10049252B2

公开(公告)日：2018-08-14

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Hsing-Lung Shen

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498 ,  G06F3/041

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

公开(公告)号：US09997473B2

公开(公告)日：2018-06-12

申请号：US15409289

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/52 ,  H01L21/54 ,  H01L23/18 ,  H01L23/055 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.