公开(公告)号：US20050110110A1

公开(公告)日：2005-05-26

申请号：US10721524

申请日：2003-11-25

Applicant: Richard Blanchard ,  Joseph McAlexander

Inventor： Richard Blanchard ,  Joseph McAlexander

IPC: G01P15/135 ,  B81B3/00 ,  B81C1/00 ,  G01K5/62 ,  G01P15/18 ,  H01L21/8238 ,  H01L29/82

CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81B2203/033 ,  B81C2201/0109 ,  B81C2201/014

Abstract: A released beam structure fabricated in trench and manufacturing method thereof are provided herein. One embodiment of a released beam structure according to the present invention comprises a semiconductor substrate, a trench, a first conducting layer, and a beam. The trench extends into the semiconductor substrate and has walls. The first conducting layer is positioned over the walls of the trench at selected locations. The beam is positioned with the trench and is connected at a first portion thereof to the semiconductor substrate and movable at a second portion thereof. The second portion of the beam is spaced from the walls of the trench by a selected distance. Therefore, the second portion of the beam is free to move in a plane that is perpendicular or parallel to the surface of the substrate, and could be deflected to electrically contact with the walls of the trench in response to a predetermined acceleration force or a predetermined temperature variation applied on the beam structure. Other beam structures such as a beam held at both ends, or a beam held in the middle are also possible. Several beam structures at different angles can be fabricated simultaneously and mechanical etching stops are automatically formed to prevent unwanted overstress conditions when manufacturing several beam structures at the same time. Beam structures can also be manufactured in three orthogonal directions, providing information on acceleration in any direction.

Abstract translation: 本发明提供一种以沟槽制造的释放的束结构及其制造方法。 根据本发明的释放的光束结构的一个实施例包括半导体衬底，沟槽，第一导电层和光束。 沟槽延伸到半导体衬底中并具有壁。 第一导电层位于沟槽的选定位置的上方。 光束与沟槽定位并且在其第一部分处连接到半导体衬底并且可在其第二部分移动。 梁的第二部分与沟槽的壁间隔一定距离。 因此，梁的第二部分在垂直于或平行于衬底的表面的平面中自由移动，并且可以响应于预定的加速力或预定的加速力而被偏转以与沟槽的壁电接触 温度变化施加在梁结构上。 其他梁结构，例如保持在两端的梁或保持在中间的梁也是可能的。 可以同时制造不同角度的几个梁结构，并且自动形成机械蚀刻停止，以在同时制造几个梁结构时防止不想要的过应力条件。 梁结构也可以在三个正交方向上制造，提供关于任何方向上的加速度的信息。

公开(公告)号：US20040192045A1

公开(公告)日：2004-09-30

申请号：US10766629

申请日：2004-01-27

Applicant: Elm Technology Corporation.

Inventor： Glenn Joseph Leedy

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L25/50 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/075 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S438/949 ,  H01L2924/00

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US06661070B2

公开(公告)日：2003-12-09

申请号：US10193804

申请日：2002-07-11

Applicant: Andrew J. Zosel ,  Joel A. Kubby ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Jingkuang Chen ,  Alex T. Tran

Inventor： Andrew J. Zosel ,  Joel A. Kubby ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Jingkuang Chen ,  Alex T. Tran

IPC: H01L2982

CPC classification number: B81C1/00666 ,  B81B2203/058 ,  B81C2201/014 ,  B81C2201/0164 ,  B81C2201/056 ,  G02B26/0833

Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a structure on a single crystal silicon layer separated by an insulator layer from a substrate layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilcon forming mechanical or optical elements of the structure; exposing a selected area of the single crystal silicon layer; and releasing the formed structure.

公开(公告)号：US20030223535A1

公开(公告)日：2003-12-04

申请号：US10385386

申请日：2003-03-07

Inventor： Glenn Joseph Leedy

IPC: G21K005/00

CPC classification number: H01L25/50 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/075 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S438/949 ,  H01L2924/00

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US06602428B2

公开(公告)日：2003-08-05

申请号：US09991986

申请日：2001-11-26

Applicant: Hiroyuki Wado ,  Makiko Sugiura ,  Toshimasa Yamamoto ,  Yukihiro Takeuchi ,  Yasushi Kohno

Inventor： Hiroyuki Wado ,  Makiko Sugiura ,  Toshimasa Yamamoto ,  Yukihiro Takeuchi ,  Yasushi Kohno

IPC: H01L2100

CPC classification number: G01F1/6845 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00182 ,  B81C2201/014 ,  B81C2201/0169 ,  G01L9/0042

Abstract: A sensor for measuring a physical amount such as an amount of air includes a membrane structure composed of metal stripes sandwiched between first and second insulating layers. A metal layer made of platinum or the like is formed on the first insulating layer and then heat-treated to improve its properties. Then, the metal layer is etched into a form of the metal stripes. The second insulating layer made of a material such as silicon dioxide is formed on the etched metal stripes. Since the metal layer is heat-treated before it is etched into the form of metal stripes, the metal stripes are not deformed by the heat-treatment. The second insulating layer can be formed on the metal stripes without generating cracks in the second insulating layer.

公开(公告)号：US06544810B1

公开(公告)日：2003-04-08

申请号：US09652615

申请日：2000-08-31

Applicant: Daniel J. Koch ,  Paul L. Bergstrom

Inventor： Daniel J. Koch ,  Paul L. Bergstrom

IPC: H01L2100

CPC classification number: B81C1/00246 ,  B81B2201/025 ,  B81C2201/014 ,  B81C2203/0735

Abstract: A capacitively sensed micromachined component includes an electrically insulative substrate (120) having a first side (121) and a second side (122) opposite the first side. The component also includes a first layer (130) adjacent to the second side of the electrically insulative substrate where at least a first portion of the first layer located adjacent to the second side of the electrically insulative substrate is infra-red light absorbing and is also electrically conductive. The component further includes a diffusion and chemical barrier layer (240) encapsulating the first layer and the electrically insulative substrate. The component still further includes a capacitively sensed micromachined device (310) on the diffusion and chemical barrier layer.

Abstract translation: 电容感测的微加工部件包括具有第一侧（121）和与第一侧相对的第二侧（122）的电绝缘衬底（120）。 该部件还包括与电绝缘基板的第二侧相邻的第一层（130），其中位于电绝缘基板的第二侧附近的第一层的至少第一部分是红外光吸收，并且还 导电。 该组件还包括封装第一层和电绝缘衬底的扩散化学阻挡层（240）。 该部件还包括在扩散和化学阻挡层上的电容感应的微加工器件（310）。

公开(公告)号：US20020197873A1

公开(公告)日：2002-12-26

申请号：US09891105

申请日：2001-06-25

Inventor： Bruce Polson ,  Nan Zhang ,  Howard P. Wilson

IPC: H01L021/311

CPC classification number: B81C1/00873 ,  B81C2201/014

Abstract: A microelectromechanical (MEMS) device and a method of fabricating a MEMS device are provided. The method of fabricating the MEMS device includes the steps of: etching a die release trench in a primary handle layer of a wafer having the handle layer, an etch-stop layer disposed on the primary handle layer, and a device layer disposed on the etch-stop layer; patterning a release trench in the device layer that is aligned with the release trench in the primary handle layer; temporarily attaching an additional handle layer to the primary handle layer; etching the device layer to define a structure in the device layer; removing the etch-stop layer; and removing the additional handle layer to release the die.

Abstract translation: 提供了一种微机电（MEMS）器件和MEMS器件的制造方法。 制造MEMS器件的方法包括以下步骤：蚀刻具有手柄层的晶片的主手柄层中的裸片释放沟槽，设置在主手柄层上的蚀刻停止层以及设置在蚀刻上的器件层 停留层 图案化在与主手柄层中的释放沟槽对准的器件层中的释放沟槽; 临时附加手柄层到主手柄层; 蚀刻器件层以限定器件层中的结构; 去除蚀刻停止层; 并移除附加手柄层以释放模具。

公开(公告)号：US06484578B2

公开(公告)日：2002-11-26

申请号：US09398719

申请日：1999-09-20

Applicant: James R. Woodruff ,  Steven A. Foote

Inventor： James R. Woodruff ,  Steven A. Foote

IPC: G01P1508

CPC classification number: B81B3/0081 ,  B81B2201/0235 ,  B81C2201/014 ,  B81C2201/019 ,  G01P1/023 ,  G01P15/0802 ,  G01P15/097 ,  G01P2015/0814 ,  G01P2015/0828

Abstract: A pendulous accelerometer wherein the active reaction mass is pendulously mounted external to a fixed support structure and may include sensor cover of covers in the total active reaction mass.

Abstract translation: 一种下摆加速度计，其中所述活性反应物质被下摆地安装在固定的支撑结构外部，并且可以包括在所述总活性反应物质中的盖的传感器盖。

公开(公告)号：US20020070195A1

公开(公告)日：2002-06-13

申请号：US09991986

申请日：2001-11-26

Inventor： Hiroyuki Wado ,  Makiko Sugiura ,  Toshimasa Yamamoto ,  Yukihiro Takeuchi ,  Yasushi Kohno

IPC: C23F001/00

CPC classification number: G01F1/6845 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00182 ,  B81C2201/014 ,  B81C2201/0169 ,  G01L9/0042

Abstract: A sensor for measuring a physical amount such as an amount of air includes a membrane structure composed of metal stripes sandwiched between first and second insulating layers. A metal layer made of platinum or the like is formed on the first insulating layer and then heat-treated to improve its properties. Then, the metal layer is etched into a form of the metal stripes. The second insulating layer made of a material such as silicon dioxide is formed on the etched metal stripes. Since the metal layer is heat-treated before it is etched into the form of metal stripes, the metal stripes are not deformed by the heat-treatment. The second insulating layer can be formed on the metal stripes without generating cracks in the second insulating layer.

Abstract translation: 用于测量诸如空气量的物理量的传感器包括由夹在第一和第二绝缘层之间的金属条构成的膜结构。 在第一绝缘层上形成由铂等制成的金属层，然后进行热处理以改善其性能。 然后，金属层被蚀刻成金属条纹的形式。 在蚀刻的金属条纹上形成由诸如二氧化硅的材料制成的第二绝缘层。 由于金属层在被蚀刻成金属条纹之前被热处理，金属条不会因热处理而变形。 可以在金属条上形成第二绝缘层，而不会在第二绝缘层中产生裂纹。

公开(公告)号：US20020055260A1

公开(公告)日：2002-05-09

申请号：US10016894

申请日：2001-12-13

Applicant: HRL Laboratories

Inventor： Lap-Wai Chow ,  Tsung-Yuan Hsu ,  Daniel J. Hyman ,  Robert Y. Loo ,  Paul Ouyang ,  James H. Schaffner ,  Adele Schmitz ,  Robert N. Schwartz

IPC: H01L021/302

CPC classification number: B81C1/00246 ,  B81B2201/014 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735 ,  H01H1/58 ,  H01H59/0009 ,  H01H2001/0057

Abstract: A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as vias to connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude toward each other. Thus, when the contacts are moved toward each other by actuating the MEM switch, they connect firmly without obstruction. Tungsten is typically used to form vias in CMOS processes, and it makes an excellent contact material, but other via metals may also be employed as contacts. Interconnect metallization may be employed for other structural and interconnect needs of the MEM switch, and is preferably standard for the foundry and process used. Various metals and dielectric materials may be used to create the switches, but in a preferred embodiment the interconnect metal layers are aluminum and the dielectric material is SiO2, materials which are fully compatible with standard four-layer CMOS fabrication processes.