公开(公告)号：US20040192045A1

公开(公告)日：2004-09-30

申请号：US10766629

申请日：2004-01-27

Applicant: Elm Technology Corporation.

Inventor： Glenn Joseph Leedy

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L25/50 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/075 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S438/949 ,  H01L2924/00

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US20030057564A1

公开(公告)日：2003-03-27

申请号：US10222816

申请日：2002-08-19

Applicant: Elm Technology Corporation

Inventor： Glenn J. Leedy

IPC: H01L021/30 ,  H01L023/48 ,  H01L029/40

CPC classification number: G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 nullm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

公开(公告)号：US20010033030A1

公开(公告)日：2001-10-25

申请号：US09776885

申请日：2001-02-06

Applicant: Elm Technology Corporation

Inventor： Glenn J. Leedy

IPC: H01L023/48

CPC classification number: G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 nullm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract translation: 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路薄化到小于50um的厚度，并将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。

公开(公告)号：US20040132303A1

公开(公告)日：2004-07-08

申请号：US10742057

申请日：2003-12-18

Applicant: Elm Technology Corporation

Inventor： Glenn Joseph Leedy

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US20040070063A1

公开(公告)日：2004-04-15

申请号：US10672961

申请日：2003-09-26

Applicant: Elm Technology Corporation

Inventor： Glenn J. Leedy

IPC: H01L023/02

CPC classification number: G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 nullm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

公开(公告)号：US20030173608A1

公开(公告)日：2003-09-18

申请号：US10379820

申请日：2003-03-03

Applicant: Elm Technology Corporation

Inventor： Glenn J. Leedy

IPC: H01L027/108

CPC classification number: G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 nullm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract translation: 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，降低成本3DS存储器的制造涉及将存储器电路的薄型化到小于50um的厚度，并将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。

公开(公告)号：US20020135075A1

公开(公告)日：2002-09-26

申请号：US10144791

申请日：2002-05-15

Applicant: Elm Technology Corporation

Inventor： Glenn J. Leedy

IPC: H01L029/40

CPC classification number: G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 nullm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract translation: 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路薄化到小于50um的厚度，并将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。

公开(公告)号：US20040150068A1

公开(公告)日：2004-08-05

申请号：US10742282

申请日：2003-12-19

Applicant: Elm Technology Corporation

Inventor： Glenn Joseph Leedy

IPC: H01L029/00

CPC classification number: H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

公开(公告)号：US20020014673A1

公开(公告)日：2002-02-07

申请号：US09775670

申请日：2001-02-05

Applicant: Elm Technology Corporation

Inventor： Glenn Joseph Leedy

IPC: H01L021/00 ,  H01L029/82

CPC classification number: H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US20020005729A1

公开(公告)日：2002-01-17

申请号：US09946552

申请日：2001-09-06

Applicant: Elm Technology Corporation.

Inventor： Glenn Leedy

IPC: G01R031/02

CPC classification number: G01R31/2867 ,  G01R1/07307 ,  G01R1/07314 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/2868 ,  G01R31/2874 ,  G01R31/2886 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G01R31/31912 ,  G02F1/13452 ,  G03F7/70466 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/67138 ,  H01L21/67706 ,  H01L21/67721 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L22/22 ,  H01L23/498 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/75 ,  H01L2224/7565 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A single gas tight system which performs multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming and binning of integrated circuits. A system according to one embodiment of the present invention includes: (a) a gas tight chamber having (1) a plurality of modules each having a holding fixture, a wafer, a probing device, an electronic circuit board, and a temperature control device, (2) a gas source for supplying non-oxidizing gases such as nitrogen and hydrogen into the chamber, (3) a handler for moving the wafers and the probing devices, and (b) a computer coupled to the chamber for controlling and communicating with the handler, the temperature control devices, the holding fixtures and the probing devices. A holding fixture holds a wafer having integrated circuits and aligns the wafer to a probing device. An integrated circuit has a plurality of conductive contact portions that are able to be connected to probe points of the probing device. A temperature control device is used to heat the wafer during an oxide reduction process or during burn-in of the wafer. During the oxide reduction process, hydrogen is introduced into the chamber, and the wafer is heated so that the oxides on the contact pads can combine with hydrogen to form water vapor, thus reducing the thickness of the oxides. The computer analyzes the test and/or burn-in data and provides control signals for repairing or programming the integrated circuits. The computer system also generates a database that contains the performance data of all the integrated circuits on the wafer that are tested and allows for immediate feedback of the quality of the integrated circuits.

Abstract translation: 单个气密系统，其执行多功能，包括减小接触垫上的氧化物的厚度以及集成电路的探测，测试，老化，修复，编程和分组。 根据本发明的一个实施例的系统包括：（a）气密室，其具有（1）多个模块，每个模块具有保持夹具，晶片，探测装置，电子电路板和温度控制装置 ，（2）用于向室供应非氧化性气体例如氮气和氢气的气源，（3）用于移动晶片和探测装置的处理器，以及（b）耦合到室的计算机，用于控制和通信 处理器，温度控制装置，夹具和探测装置。 保持夹具保持具有集成电路的晶片，并将晶片对准探测装置。 集成电路具有能够连接到探测装置的探针点的多个导电接触部分。 温度控制装置用于在氧化物还原过程期间或在晶片的老化期间加热晶片。 在氧化还原过程中，将氢气引入室中，并且加热晶片，使得接触焊盘上的氧化物可以与氢气结合形成水蒸气，从而减小氧化物的厚度。 计算机分析测试和/或老化数据，并提供用于修复或编程集成电路的控制信号。 计算机系统还生成包含被测试的晶片上所有集成电路的性能数据的数据库，并允许对集成电路的质量的即时反馈。