公开(公告)号：US20130007562A1

公开(公告)日：2013-01-03

申请号：US13175610

申请日：2011-07-01

Applicant: Anthony Fai ,  Nir Jacob Wakrat ,  Nicholas Seroff

Inventor： Anthony Fai ,  Nir Jacob Wakrat ,  Nicholas Seroff

IPC: G06F11/08 ,  G06F13/00

CPC classification number: G06F11/1004

Abstract: In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Abstract translation: 在一个实现中，存储器设备包括非易失性存储器，通过第一总线通信地耦合到非易失性存储器的存储器控​​制器以及存储器控制器经由第二总线与主机设备通信的主机接口。 存储器装置还可以包括主机接口的信号调节器，其适于根据从主机设备接收的信号电平数据调节信号以调整在第二总线上接收的信号的信号电平，其中信号电平数据与电压电平相关 的由主机设备生成的信号，以对通过第二总线发送的数据进行编码。

公开(公告)号：US20120331370A1

公开(公告)日：2012-12-27

申请号：US13167764

申请日：2011-06-24

Applicant: Zongwang Li ,  Wu Chang ,  Chung-Li Wang ,  Changyou Xu ,  Shaohua Yang ,  Yang Han

Inventor： Zongwang Li ,  Wu Chang ,  Chung-Li Wang ,  Changyou Xu ,  Shaohua Yang ,  Yang Han

IPC: G06F11/08

CPC classification number: H04L1/0047 ,  H03M13/1171 ,  H03M13/134 ,  H03M13/255

Abstract: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

Abstract translation: 本发明的各种实施例提供了用于数据处理的系统和方法。 公开了一种数据处理电路，其包括：数据检测器电路，第一符号约束布置电路和第二符号约束布置电路。 数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合，以产生包括多个非二进制符号的检测输出。 第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。 来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。 第二符号约束排列电路可操作以接收第二输入数据集并且根据第二布置算法重新布置第二数据输入以产生解码的数据集。 用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

公开(公告)号：US20120324311A1

公开(公告)日：2012-12-20

申请号：US13600077

申请日：2012-08-30

Applicant: David Flynn ,  Bert Lagerstedt ,  John Strasser ,  Jonathan Thatcher ,  Michael Zappe

Inventor： David Flynn ,  Bert Lagerstedt ,  John Strasser ,  Jonathan Thatcher ,  Michael Zappe

IPC: H03M13/05 ,  G06F11/08 ,  G11C16/02

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/02 ,  H04L67/1097 ,  H05K7/1444 ,  H05K7/1487 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.

Abstract translation: 公开了用于管理固态存储设备中的数据的装置，系统和方法。 包括固态存储和固态控制器。 固态存储控制器包括写数据流水线和读数据管线。写数据流水线包括打包器和ECC发生器。 打包器接收数据段并创建一个或多个数据包，以便固态存储。 ECC发生器为从分组器接收到的数据分组生成一个或多个纠错码（ECC）。 读取数据流水线包括ECC校正模块，解包器和对准模块。 ECC校正模块从固态存储读取数据包，使用对应的ECC确定是否存在数据错误，并纠正错误。 拆包器检查并删除一个或多个数据包头。 对齐模块删除不需要的数据，并将数据重新格式化为对象的数据段。

公开(公告)号：US20120324275A1

公开(公告)日：2012-12-20

申请号：US13593997

申请日：2012-08-24

Applicant: JASON K. RESCH ,  S. CHRISTOPHER GLADWIN

Inventor： JASON K. RESCH ,  S. CHRISTOPHER GLADWIN

IPC: G06F11/08

CPC classification number: G06F11/1076 ,  G06F3/0629 ,  G06F3/064 ,  G06F3/067 ,  G06F11/2094 ,  G06F12/0646 ,  G06F17/30073 ,  G06F17/30082 ,  G06F17/30085 ,  G06F17/30117 ,  H04L67/1097

Abstract: A dispersed storage device for use within a dispersed storage network operates to select a set of dispersed storage units for storage of a data object by slicing an encoded data segment of a data object into error coded data slices, determining slice metadata for the error coded data slices, determining memory characteristics of dispersed storage units capable of storing the error coded data slices and selecting the set of dispersed storage units for storing the error coded data slices based on the slice metadata and the memory characteristics.

Abstract translation: 用于分散存储网络中的分散存储设备通过将数据对象的编码数据段分片成错误编码数据片段来选择一组分散存储单元以存储数据对象，确定错误编码数据的片元数据 确定能够存储错误编码数据片的分散存储单元的存储器特征，并且基于片元数据和存储器特征选择用于存储错误编码数据片的分散存储单元组。

公开(公告)号：US20120311376A1

公开(公告)日：2012-12-06

申请号：US13154299

申请日：2011-06-06

Applicant: Viktoriya Taranov ,  Alexander Hopmann ,  Antonio Marcos Da Silva, JR. ,  Nikita Voronkov ,  Kai Yiu Luk ,  Ramanathan Somasundaram ,  Artsiom Kokhan ,  Siddharth Rajendra Shah ,  Daniel Blood ,  Bhavesh Doshi

Inventor： Viktoriya Taranov ,  Alexander Hopmann ,  Antonio Marcos Da Silva, JR. ,  Nikita Voronkov ,  Kai Yiu Luk ,  Ramanathan Somasundaram ,  Artsiom Kokhan ,  Siddharth Rajendra Shah ,  Daniel Blood ,  Bhavesh Doshi

IPC: G06F11/16 ,  G06F11/08 ,  G06F17/30

CPC classification number: G06F17/30578 ,  G06F11/1448 ,  G06F11/1471 ,  G06F11/2023 ,  G06F11/2033 ,  G06F11/2038 ,  G06F11/2048 ,  G06F11/2097 ,  G06F2201/80

Abstract: A secondary location of a network acts as a recovery network for a primary location of the service. The secondary location is maintained in a warm state that is configured to replace the primary location in a case of a failover. During normal operation, the primary location actively services user load and performs backups that include full backups, incremental backups and transaction logs that are automatically replicated to the secondary location. Information is stored (e.g. time, retry count) that may be used to assist in determining when the backups are restored correctly at the secondary location. The backups are restored and the transaction logs are replayed at the secondary location to reflect changes (content and administrative) that are made to the primary location. After failover to the secondary location, the secondary location becomes the primary location and begins to actively service the user load.

Abstract translation: 网络的辅助位置充当服务的主要位置的恢复网络。 辅助位置保持在暖状态，配置为在故障切换的情况下替换主位置。 在正常操作期间，主要位置主动地为用户加载并执行备份，其中包括自动复制到辅助位置的完整备份，增量备份和事务日志。 存储信息（例如，时间，重试计数），其可以用于帮助确定何时在次要位置正确恢复备份。 恢复备份，并在次要位置重播事务日志，以反映对主位置进行的更改（内容和管理）。 故障切换到辅助位置后，辅助位置将成为主要位置，并开始主动为用户负载服务。

公开(公告)号：US20120290885A1

公开(公告)日：2012-11-15

申请号：US13106040

申请日：2011-05-12

Applicant: Mohammad Mobin ,  Matthew Tota ,  Gregory Winn

Inventor： Mohammad Mobin ,  Matthew Tota ,  Gregory Winn

IPC: G06F11/08

CPC classification number: H04L7/0337

Abstract: In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.

Abstract translation: 在所描述的实施例中，收发器支持使用过采样时钟和数据恢复（CDR）电路采用具有预定CDR采样时钟的高速率数据采样的两个或更多个速率。 定时恢复电路检测并考虑过采样较低速率数据时的额外或缺失样本。 边缘检测器检测每个实际数据符号边缘并提供当前时刻的样本块中的边缘判定偏移。 从前一时刻的实际和计算边缘产生边缘错误; 并且生成当前和前一时刻的实际边缘之间的边缘距离。 滤波边缘距离和误差被组合以产生用于当前时刻的数据符号边缘的计算边缘位置。 边缘判定偏移被应用于当前计算的边缘位置以识别采样值，以产生用于数据符号来检测当前数据值的决定。

公开(公告)号：US20120278677A1

公开(公告)日：2012-11-01

申请号：US13532300

申请日：2012-06-25

Applicant: Yoshinobu Kure ,  Masato Kawada

Inventor： Yoshinobu Kure ,  Masato Kawada

IPC: H03M13/03 ,  G06F11/08

CPC classification number: H04L1/1877 ,  H04L1/0002 ,  H04L1/0006 ,  H04L1/0009 ,  H04L1/1816

Abstract: A packet transmission apparatus to transmit a packet limited in arrival deadline through a best-effort network includes a packet automatic retransmission section to control retransmission of an undelivered packet, a forward error correction coding section to add redundant packet to a data packet block, and a redundancy determining section to dynamically determine redundancy of the redundant packet based on observed network state information so that a loss rate after error correction at a receiver achieved by only the retransmission of the undelivered packet satisfies an allowable loss rate after error correction.

Abstract translation: 通过尽力而为网络发送限时到达限制的分组的分组发送装置包括：控制未传送分组的重发的分组自动重传部，向数据分组块添加冗余分组的前向纠错编码部， 冗余确定部分，用于基于观察到的网络状态信息动态地确定冗余分组的冗余，使得仅通过未传送分组的重传获得的接收机进行纠错之后的丢失率在纠错之后满足允许的损失率。

公开(公告)号：US20120266019A1

公开(公告)日：2012-10-18

申请号：US13534435

申请日：2012-06-27

Applicant: Siew Yong Sim-Tang

Inventor： Siew Yong Sim-Tang

IPC: G06F11/08

CPC classification number: G06F11/2097 ,  G06F11/1469 ,  G06F11/1471 ,  G06F11/2094 ,  G06F2201/82 ,  G06F2201/84

Abstract: A data management system (“DMS”) provides an automated, continuous, real-time, substantially no downtime data protection service to one or more data sources. A host driver embedded in an application server captures real-time data transactions, preferably in the form of an event journal. The driver functions to translate traditional file/database/block I/O and the like into a continuous, application-aware, output data stream. The host driver includes an event processor that can perform a recovery operation to an entire data source or a subset of the data source using former point-in-time data in the DMS. The recovery operation may have two phases. First, the structure of the host data in primary storage is recovered to the intended recovering point-in-time. Thereafter, the actual data itself is recovered. The event processor enables such data recovery in an on-demand manner, by allowing recovery to happen simultaneously while an application accesses and updates the recovering data.

公开(公告)号：US20120240007A1

公开(公告)日：2012-09-20

申请号：US13277876

申请日：2011-10-20

Applicant: Richard D. BARNDT ,  Xinde HU ,  Anthony D. WEATHERS

Inventor： Richard D. BARNDT ,  Xinde HU ,  Anthony D. WEATHERS

IPC: H03M13/09 ,  G06F12/02 ,  G06F11/08

CPC classification number: H03M13/1111 ,  H03M13/1108 ,  H03M13/1128 ,  H03M13/3707

Abstract: A solid state storage device includes a flash memory and a controller configured to store data in the flash memory via a plurality of channels. The stored data is encoded using a low-density parity-check code. Hard-decision decoders are configured to decode encoded data received from the flash memory via respective channels of the plurality of channels using the low-density parity-check code and to provide decoded data to the controller in response to one or more read commands from the controller. A soft-decision decoder is configured to decode the encoded data received from the flash memory using the low-density parity-check code and to provide the decoded data to the controller in response to one of the plurality of hard-decision decoders failing to decode the encoded data. The encoded data is obtained by the soft-decision decoder using a plurality of read-retry operations.

Abstract translation: 固态存储装置包括闪速存储器和被配置为经由多个通道将数据存储在闪速存储器中的控制器。 存储的数据使用低密度奇偶校验码进行编码。 硬判决解码器被配置为使用低密度奇偶校验码对多个信道中的相应信道从闪速存储器接收的编码数据进行解码，并且响应于来自所述多个信道的一个或多个读取命令向控制器提供解码数据 控制器。 软判决解码器被配置为使用低密度奇偶校验码对从闪速存储器接收的编码数据进行解码，并且响应于多个硬判决解码器中的一个不能解码而将解码数据提供给控制器 编码数据。 编码数据由软判决解码器使用多个读 - 重试操作获得。

公开(公告)号：US20120240006A1

公开(公告)日：2012-09-20

申请号：US13118137

申请日：2011-05-27

Applicant: Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

Inventor： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

IPC: H03M13/15 ,  G06F11/16 ,  G06F11/08

CPC classification number: H03M13/256 ,  G06F11/1072 ,  H03M13/253 ,  H03M13/2933 ,  H03M13/3988

Abstract: A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

Abstract translation: 描述了用于在多级单元（MLC）闪速存储器件中存储数据的方法和系统。 所述方法包括接收用于存储在闪存设备中的数据，所述闪存设备包括MLC闪存单元阵列，并且根据网格编码的调制方案将接收到的数据编码为非二进制符号。 该方法还包括将每个非二进制符号写入相应的闪存单元组，其中每个快闪存储器单元组包括多个MLC闪存单元。