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    Adaptive-biased mixer
    121.
    发明授权
    Adaptive-biased mixer 有权
    自适应偏置混频器

    公开(公告)号：US07356317B2

    公开(公告)日：2008-04-08

    申请号：US10890712

    申请日：2004-07-14

    申请人： Zhiwei Xu ,  Pei-Ming Daniel Chow ,  M. Frank Chang

    发明人： Zhiwei Xu ,  Pei-Ming Daniel Chow ,  M. Frank Chang

    IPC分类号： H04B1/10 ,  H04B1/26

    CPC分类号： H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1491 ,  H03D7/165 ,  H03D2200/0043 ,  H03D2200/0047 ,  H03D2200/0084

    摘要： A system or method for a circuit network that receives an RF signal, and where a plurality of switching transistors receive an RF signal output by the circuit network and perform mixing with a local oscillation (LO) signal received on a LO input. An active bias circuit performs active bias of the plurality of switching transistors in a feedback loop provided between the LO input and an output of the plurality of switching transistors.

    摘要翻译： 一种用于接收RF信号的电路网络的系统或方法，其中多个开关晶体管接收由电路网络输出的RF信号，并且与在LO输入端接收的本地振荡（LO）信号进行混频。 有源偏置电路在LO输入和多个开关晶体管的输出之间的反馈环路中执行多个开关晶体管的有源偏置。

    Sense amplifier for low voltage high speed sensing
    122.
    发明授权
    Sense amplifier for low voltage high speed sensing 有权
    用于低电压高速感应的感应放大器

    公开(公告)号：US07345512B2

    公开(公告)日：2008-03-18

    申请号：US10838999

    申请日：2004-05-04

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    IPC分类号： G01R19/00

    CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062

    摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

    摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。

    Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation
    123.
    发明授权
    Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation 有权
    埋入位线非挥发性浮动栅极存储单元，其具有沟槽中的独立可控制控制栅极及其阵列，以及形成方法

    公开(公告)号：US07307308B2

    公开(公告)日：2007-12-11

    申请号：US10797296

    申请日：2004-03-09

    申请人： Dana Lee ,  Bomy Chen ,  Sohrab Kianian

    发明人： Dana Lee ,  Bomy Chen ,  Sohrab Kianian

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

    摘要： A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.

    摘要翻译： 掩埋位线读/程序非易失性存储单元和阵列能够实现高密度。 电池和阵列由具有多个间隔开的沟槽的半导体衬底制成，沟槽之间具有平坦表面。 每个沟槽都有一个侧壁和一个底壁。 每个存储单元具有用于存储其上的电荷的浮动栅极。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有两个部分。 源/漏区中的一个位于沟槽的底壁。 浮动栅极在沟槽中，并且在沟槽的第一部分之上并且与沟槽的侧壁间隔开。 栅电极控制在衬底的平面中的第二部分中的沟道的导通。 另一个源极/漏极区域位于衬底的平面表面中的衬底中。 独立可控的控制栅极也在沟槽中，与浮动栅极绝缘并且与其电容耦合。 通过热通道电子注入的电池程序，并且通过Fowler-Nordheim将电子从浮栅隧穿到栅电极或从浮栅到沟槽底壁处的源极/漏极区擦除。 源极，漏极和控制栅极都基本上彼此平行，栅电极基本上垂直于源极/漏极/控制栅极。 源极/漏极线被埋在衬底中，形成虚拟接地阵列。

    High-speed and low-power differential non-volatile content addressable memory cell and array
    127.
    发明授权
    High-speed and low-power differential non-volatile content addressable memory cell and array 有权
    高速和低功耗差分非易失性内容可寻址存储单元和阵列

    公开(公告)号：US07196921B2

    公开(公告)日：2007-03-27

    申请号：US10893811

    申请日：2004-07-19

    申请人： Vishal Sarin ,  Hieu Van Tran ,  Isao Nojima

    发明人： Vishal Sarin ,  Hieu Van Tran ,  Isao Nojima

    IPC分类号： G11C15/00

    CPC分类号： G11C14/00 ,  G11C15/046

    摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.

    摘要翻译： 差分非易失性内容可寻址存储器阵列具有使用一对非易失性存储元件的差分非易失性内容可寻址存储器单元。 每个非易失性存储元件可以是分离栅极浮栅晶体管或堆叠栅极浮栅晶体管，其具有第一端子，第二端子，其间的沟道以及通道的至少一部分上的浮置栅极以控制 通道中的电子传导，以及控制栅极。 浮置栅极存储晶体管可以处于以下两种状态之一：电流可以在第一端子和第二端子之间流动的第一状态，例如擦除，以及第二状态，诸如编程的，其中基本上没有电流流动 在第一端子和第二端子之间。 一对差分比较数据线连接到该对非易失性浮栅晶体管中的每一个的控制栅极。 匹配线将一对非易失性浮栅晶体管的每一个的第一端连接到第一电压。 最后，每个存储元件的第二端子被连接到与第一电压不同的第二电压。 通过存储单元的电流表示比较数据线的内容与存储元件的内容之间的错误匹配。

    Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation
    128.
    发明授权
    Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation 有权
    具有独立可控制控制栅极的双向读/写非易失性浮栅存储单元及其阵列及其形成方法

    公开(公告)号：US07190018B2

    公开(公告)日：2007-03-13

    申请号：US10409407

    申请日：2003-04-07

    申请人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

    发明人： Bomy Chen ,  Sohrab Kianian ,  Jack Frayer

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115

    摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.

    摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 独立可控的控制栅极与源极/漏极区域中的每一个绝缘，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 独立可控的控制门允许这种存储器单元的阵列在NAND配置中操作。

    Method of manufacturing an isolation-less, contact-less array of bi-directional read/program non-volatile floating gate memory cells with independent controllable control gates
    129.
    发明授权
    Method of manufacturing an isolation-less, contact-less array of bi-directional read/program non-volatile floating gate memory cells with independent controllable control gates 有权
    制造具有独立可控制控制门的双向读/非易失性浮动栅极存储单元的无隔离，无接触阵列的方法

    公开(公告)号：US07183163B2

    公开(公告)日：2007-02-27

    申请号：US10824016

    申请日：2004-04-13

    申请人： Dana Lee ,  Bomy Chen

    发明人： Dana Lee ,  Bomy Chen

    IPC分类号： H01L29/788 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

    摘要： A method of making an isolation-less, contact-less array of bi-directional read/program non-volatile memory cells is disclosed. Each memory cell has two stacked gate floating gate transistors, with a switch transistor there between. The source/drain lines of the cells and the control gate lines of the stacked gate floating gate transistors in the same column are connected together. The gate of the switch transistors in the same row are connected together. Spaced apart trenches are formed in a substrate in a first direction. Floating gates are formed in the trenches, along the side wall of the trenches. A buried source/bit line is formed at the bottom of each trench. A control gate common to both floating gates is also formed in each trench insulated from the floating gates, capacitively coupled thereto, and insulated from the buried source/bit line. Transistor gates parallel to one another are formed in a second direction, substantially perpendicular to the first direction on the planar surface of the substrate. In one embodiment, openings between the rows of transistor gates are used to cut the floating gates in the trenches, without cutting the control gates.

    摘要翻译： 公开了制造双向读/程序非易失性存储单元的无隔离，无接触阵列的方法。 每个存储单元具有两个堆叠栅极浮栅晶体管，其间具有开关晶体管。 单元的源极/漏极线和同一列中的堆叠栅极浮置栅极晶体管的控制栅极线连接在一起。 同一行的开关晶体管的栅极连接在一起。 在第一方向上在基板上形成间隔开的沟槽。 沿着沟槽的侧壁在沟槽中形成浮动栅极。 在每个沟槽的底部形成埋入的源极/位线。 两个浮动栅极共用的控制栅极也形成在与浮动栅极绝缘的每个沟槽中，电容耦合到该栅极并且与掩埋源极/位线绝缘。 在彼此平行的晶体管栅极形成在基板的平坦表面上基本上垂直于第一方向的第二方向上。 在一个实施例中，晶体管栅极行之间的开口用于切割沟槽中的浮动栅极而不切断控制栅极。

    Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system
    130.
    发明授权
    Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system 有权
    寻求窗口验证程序系统和方法，用于多级非易失性存储器集成电路系统

    公开(公告)号：US07149110B2

    公开(公告)日：2006-12-12

    申请号：US10737689

    申请日：2003-12-15

    申请人： Hieu Van Tran ,  Hung Q. Nguyen ,  Amitay Levi ,  Isao Nojima

    发明人： Hieu Van Tran ,  Hung Q. Nguyen ,  Amitay Levi ,  Isao Nojima

    IPC分类号： G11C11/34

    CPC分类号： G11C13/0064 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2013/0054 ,  G11C2211/5634

    摘要： A memory comprises a plurality of digital multilevel memory cells. A window of valid data voltages for accessing the said plurality of digital multilevel memory cells is detected. The window may be detected by incrementing a first programming voltage to program data in the plurality of memory cells and verifying whether the data in at least one of said plurality of memory cells is properly programmed. The incrementing and verifying may be repeated until data is verified to be properly programmed in one of said plurality of memory cells. The data in each memory cell of said plurality of memory cells is verified. The verification may be by incrementing a second programming voltage, and verifying whether data in each memory cell is properly programmed within a margin. The incrementing and verifying is repeated for each memory cell outside of the margin.

    摘要翻译： 存储器包括多个数字多电平存储器单元。 检测用于访问所述多个数字多电平存储器单元的有效数据电压的窗口。 可以通过将第一编程电压递增到多个存储器单元中的程序数据并且验证所述多个存储器单元中的至少一个中的数据是否被适当地编程来检测窗口。 可以重复递增和验证直到数据被验证为在所述多个存储器单元之一中被适当地编程。 验证所述多个存储单元的每个存储单元中的数据。 验证可以通过增加第二编程电压，并验证每个存储器单元中的数据是否在一定的范围内被适当地编程。 对边缘外的每个存储单元重复递增和验证。