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    Tandem interleaver
    121.
    发明授权
    Tandem interleaver 失效
    串联交织器

    公开(公告)号：US06639707B2

    公开(公告)日：2003-10-28

    申请号：US10016362

    申请日：2001-11-30

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: G02F103

    CPC classification number: G02B6/29302 ,  G02B6/272 ,  G02B6/2766 ,  G02B6/2773 ,  G02B6/29386

    Abstract: A low dispersion comb filter or interleaver comprises a first birefringent element assembly having at least one birefringent element and a second birefringent element assembly having at least one other birefringent element. The first birefringent element assembly and the second birefringent element assembly are configured so as to cooperate with one another in a manner which mitigates dispersion of the interleaver. By aligning the polarization directions of the odd channels and the even channels so as to be parallel with respect to one another prior to entering the second birefringent element assembly, zero or nearly zero dispersion is obtained simultaneously for both the odd and even channels.

    Abstract translation: 低色散梳状滤波器或交织器包括具有至少一个双折射元件的第一双折射元件组件和具有至少一个其它双折射元件的第二双折射元件组件。 第一双折射元件组件和第二双折射元件组件被配置为以减轻交错器的色散的方式彼此协作。 通过使奇数通道和偶数通道的偏振方向在进入第二双折射元件组件之前相对彼此平行对准，对奇数和偶数通道同时获得零或接近零的色散。

    Method for fabricating on-chip inductors and related structure
    122.
    发明授权
    Method for fabricating on-chip inductors and related structure 有权
    制造片上电感器及相关结构的方法

    公开(公告)号：US06396122B1

    公开(公告)日：2002-05-28

    申请号：US09658483

    申请日：2000-09-08

    Applicant: David Howard ,  Bin Zhao ,  Q. Z. Liu

    Inventor： David Howard ,  Bin Zhao ,  Q. Z. Liu

    IPC: H01L2900

    CPC classification number: H01L28/10 ,  H01L27/08

    Abstract: According to various disclosed embodiments, a conductor is patterned in a dielectric. The conductor can be patterned, for example, in the shape of a square spiral. The conductor can comprise, for example, copper, aluminum, or copper-aluminum alloy. The dielectric can be, for example, silicon oxide or a low-k dielectric. A spin-on matrix containing high permeability particles is then deposited adjacent to the patterned conductor. The high permeability particles comprise material having a permeability substantially higher than the permeability of the dielectric. The high permeability particles can comprise, for example, nickel, iron, nickel-iron alloy, or magnetic oxide. As a result, an inductor having a high inductance value is achieved without lowering the quality factor of the inductor.

    Abstract translation: 根据各种公开的实施例，导体在电介质中图案化。 导体可以被图案化，例如，呈正方形螺旋形。 导体可以包括例如铜，铝或铜 - 铝合金。 电介质可以是例如氧化硅或低k电介质。 然后将包含高磁导率颗粒的旋涂基体沉积在图案化导体附近。 高磁导率颗粒包括具有比电介质的磁导率显着更高的磁导率的材料。 高磁导率颗粒可以包括例如镍，铁，镍 - 铁合金或磁性氧化物。 结果，实现了具有高电感值的电感器，而不降低电感器的品质因数。

    Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing
    123.
    发明授权
    Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing 有权
    与半导体集成电路制造的低介电常数绝缘体互连

    公开(公告)号：US06187672B1

    公开(公告)日：2001-02-13

    申请号：US09158337

    申请日：1998-09-22

    Applicant: Bin Zhao ,  Maureen R. Brongo

    Inventor： Bin Zhao ,  Maureen R. Brongo

    IPC: H01L214763

    CPC classification number: H01L21/76802 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76834

    Abstract: A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.

    Abstract translation: 提供了一种用于在半导体本体上形成改进的互连结构的方法。 第一金属层沉积在半导体本体上。 具有高度的牺牲层沉积在第一金属层上。 牺牲层和金属层被图案化以形成分离的金属线，牺牲层保留在所述金属线上。 然后沉积低k材料以填充金属线之间的间隙并覆盖牺牲层。 然后将低k材料去除到牺牲层的高度内的水平。 然后去除牺牲层。 保护层沉积在金属线和低k材料的顶部。 介电层沉积在保护层上。 保护层保护低k材料免受后续工艺步骤所用化学品的侵蚀，以蚀刻电介质层中的通孔，剥离光致抗蚀剂和清洁通孔。 然后选择性地蚀刻保护层以使通孔塞和金属线之间的接触。

    STABILIZED WHOLE GRAIN FLOUR AND METHOD OF MAKING
    126.
    发明申请
    STABILIZED WHOLE GRAIN FLOUR AND METHOD OF MAKING 审中-公开
    稳定的全谷物和制备方法

    公开(公告)号：US20140106052A1

    公开(公告)日：2014-04-17

    申请号：US13985712

    申请日：2012-02-24

    Applicant: Derwin G. Hawley ,  Edward D. Howey ,  William H. Cleaver ,  Lynn C. Haynes ,  Desiree S. Bramble ,  Ning Zhou ,  Bin Zhao ,  Timothy S. Hansen ,  Domenico R. Cassone ,  Sarwat Gabriel

    Inventor： Derwin G. Hawley ,  Edward D. Howey ,  William H. Cleaver ,  Lynn C. Haynes ,  Desiree S. Bramble ,  Ning Zhou ,  Bin Zhao ,  Timothy S. Hansen ,  Domenico R. Cassone ,  Sarwat Gabriel

    IPC: A21D6/00

    CPC classification number: A21D6/003 ,  A21D13/02 ,  A23L7/115 ,  A23L7/197 ,  B02C9/04 ,  B02C23/08

    Abstract: Stabilized whole grain flours having a fine particle size and which exhibit good baking functionality are produced with high throughput using two bran and germ fractions and an endosperm fraction. One bran and germ fraction is a coarse fraction which is subjected to two stage grinding, but the second bran and germ fraction is a low ash, fine bran and germ fraction which is sufficiently fine so that it does not need to be subjected to grinding thereby reducing starch damage and increasing production with reduced grinding equipment load. Portions of the coarse bran and germ fraction which are ground in the first grinding stage to a sufficient fineness are separated out and not subjected to additional grinding further reducing starch damage and increasing production. The bran and germ fractions may be combined, subjected to stabilization, and combined with the endosperm fraction to obtain a stabilized whole grain flour.

    Abstract translation: 使用两个麸皮和胚芽部分和胚乳部分以高产量生产具有细粒度并且表现出良好烘烤功能的稳定的全谷物面粉。 一个麸皮和胚芽部分是经过两阶段研磨的粗级分，但是第二糠和胚芽级分是足够细的低灰分，细糠和胚芽分数，从而不需要进行研磨 降低粉碎设备负荷，减少淀粉损伤并增加生产。 将在第一研磨阶段研磨的粗糠和胚芽级分的部分分离成足够的细度，并且不进行另外的研磨，进一步减少淀粉损伤并增加产量。 可以将麸皮和胚芽部分组合，进行稳定化，并与胚乳部分组合以获得稳定的全谷物粉末。

    VLPs derived from cells that do not express a viral matrix or core protein
    127.
    发明授权
    VLPs derived from cells that do not express a viral matrix or core protein 有权
    源自不表达病毒基质或核心蛋白的细胞的VLP

    公开(公告)号：US08697088B2

    公开(公告)日：2014-04-15

    申请号：US12127625

    申请日：2008-05-27

    Applicant: Gale Smith ,  Peter Pushko ,  Kutub Mahmood ,  Bin Zhao

    Inventor： Gale Smith ,  Peter Pushko ,  Kutub Mahmood ,  Bin Zhao

    IPC: A61K39/145 ,  C12N15/44

    CPC classification number: A61K39/145 ,  A61K2039/5258 ,  C07K2319/00 ,  C12N7/00 ,  C12N2710/16723 ,  C12N2760/16123

    Abstract: The present invention discloses novel influenza virus-like particles (VLPs) that contain chimeric proteins or influenza membrane proteins. The chimeric proteins are derived from fragments of influenza membrane proteins fused to heterologous proteins. The invention includes antigenic formulations and vaccines comprising VLPs of the invention as well as methods of making and administering VLPs to vertebrates, including methods of inducing immunity to infections, such as influenza.

    Abstract translation: 本发明公开了含有嵌合蛋白或流感病毒膜蛋白的新型流感病毒样颗粒（VLPs）。 嵌合蛋白质衍生自与异源蛋白质融合的流感病毒膜蛋白片段。 本发明包括抗原制剂和包含本发明的VLP的疫苗以及向脊椎动物制备和施用VLP的方法，包括诱导感染免疫的方法，例如流感。

    Serial cascade of minimium tail voltages of subsets of LED strings for dynamic power control in LED displays
    130.
    发明授权
    Serial cascade of minimium tail voltages of subsets of LED strings for dynamic power control in LED displays 有权
    用于LED显示屏中动态功率控制的LED灯串子串的最小尾电压串联级联

    公开(公告)号：US08493003B2

    公开(公告)日：2013-07-23

    申请号：US12690972

    申请日：2010-01-21

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H05B37/02

    CPC classification number: H05B33/0818 ,  H05B33/0857

    Abstract: A light emitting diode (LED) system implements a power management technique. The LED system includes a plurality of LED drivers connected in series, each LED driver configured to regulate the current flowing through a corresponding subset of a plurality of LED strings. Each LED driver determines the tail voltages of the one or more LED strings of the corresponding subset. Each LED driver, except for the first LED driver in the series, also receives a voltage representative of the minimum tail voltage of the other subsets regulated by the upstream LED drivers. Each LED driver then provides the lowest of the voltage received from the upstream LED driver and the one or more tail voltages of the corresponding subset to the downstream LED driver. In this manner a voltage representative of the minimum tail voltage of the plurality of LED strings is cascaded through the series. A feedback controller monitors the minimum tail voltage represented by this cascaded voltage and accordingly adjusts an output voltage provided to the head ends of the plurality of LED strings.

    Abstract translation: 发光二极管（LED）系统实现电源管理技术。 LED系统包括串联连接的多个LED驱动器，每个LED驱动器配置成调节流过多个LED串的相应子集的电流。 每个LED驱动器确定相应子集的一个或多个LED串的尾部电压。 除了该系列中的第一个LED驱动器之外，每个LED驱动器还接收代表由上游LED驱动器调节的其他子集的最小尾电压的电压。 然后，每个LED驱动器将从上游LED驱动器接收的最低电压和相应子集的一个或多个尾部电压提供给下游LED驱动器。 以这种方式，表示多个LED串的最小尾电压的电压通过该系列级联。 反馈控制器监视由该级联电压表示的最小尾电压，并相应地调节提供给多个LED串的头端的输出电压。

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