公开(公告)号：US08779408B2

公开(公告)日：2014-07-15

申请号：US13436203

申请日：2012-03-30

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen

IPC: H01L47/00

CPC classification number: H01L45/1273 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.

Abstract translation: 本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。 绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。 底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。 顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

公开(公告)号：US20140036570A1

公开(公告)日：2014-02-06

申请号：US13567750

申请日：2012-08-06

Applicant: Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

Inventor： Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC: G11C7/00 ,  G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2213/77

Abstract: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

Abstract translation: 提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。 存储器件的操作方法包括以下步骤。 使存储器件处于置位状态。 用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。 读取设置状态的存储器件。 一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。 将恢复的偏置电压施加到存储器件。 在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。

公开(公告)号：US20130343115A1

公开(公告)日：2013-12-26

申请号：US13601209

申请日：2012-08-31

Applicant: WEI-CHIH CHIEN ,  MING-HSIU LEE

Inventor： WEI-CHIH CHIEN ,  MING-HSIU LEE

IPC: H01L47/00 ,  G11C11/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/50008 ,  G11C2029/5002 ,  G11C2213/72 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/146

Abstract: A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.

Abstract translation: 提供了一种电阻记忆单元，包括第一电极，钨金属层，金属氧化物层和第二电极。 钨金属层设置在第一电极上。 金属氧化物层设置在钨金属层上。 第二电极包括第一连接焊盘，第二连接焊盘和电连接在第一连接焊盘和第二连接焊盘之间的桥接部分。 桥接部分设置在金属氧化物层上或围绕金属氧化物层。 电阻存储单元通过穿过金属氧化物层和钨金属层的第一电流路径或从第一连接焊盘延伸到第二连接焊盘的第二电流路径来调节金属氧化物层的电阻率。

公开(公告)号：US20130242648A1

公开(公告)日：2013-09-19

申请号：US13421718

申请日：2012-03-15

Applicant: Matthew J. BrightSky ,  Roger W. Cheek ,  Ming-Hsiu Lee

Inventor： Matthew J. BrightSky ,  Roger W. Cheek ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  H01L21/8239

CPC classification number: G11C13/0004 ,  G11C13/0033 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641 ,  H01L45/1675

Abstract: A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.

Abstract translation: 存储器芯片以及在单个晶片上制造具有不同编程性能和保持特性的存储器件的方法。 一种方法包括在晶片上沉积相变材料的第一界限区域，并在晶片上沉积相变材料的第二有界区域。 该方法包括改变相变材料的第一有界区域的开关体积的化学成分。 该方法包括在相变材料的第一有界区域中形成具有相变材料的修改的开关体积的第一存储单元，以及相变材料的第二有界区域中的第二存储单元，具有未改变的相变材料的开关体积，例如 第一存储单元具有第一保留特性，而第二存储单元具有第二保留特性。 第一保留性与第二保留性不同。

公开(公告)号：US08437192B2

公开(公告)日：2013-05-07

申请号：US12785291

申请日：2010-05-21

Applicant: Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

Inventor： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

IPC: G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C5/02 ,  G11C5/06

CPC classification number: H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

Abstract translation: 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

公开(公告)号：US08374019B2

公开(公告)日：2013-02-12

申请号：US12985253

申请日：2011-01-05

Applicant: Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

Inventor： Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC: G11C11/00

CPC classification number: H01L45/06 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C14/00 ,  G11C2013/0083 ,  G11C2013/0092 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

Abstract: A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.

Abstract translation: 一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。 预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。 设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

公开(公告)号：US08241928B2

公开(公告)日：2012-08-14

申请号：US12777858

申请日：2010-05-11

Applicant: Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L2224/73204 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.

Abstract translation: 半导体工艺测试结构包括电极，电荷俘获层和扩散区域。 测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。 然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

公开(公告)号：US20120187362A1

公开(公告)日：2012-07-26

申请号：US13436203

申请日：2012-03-30

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen

IPC: H01L45/00

CPC classification number: H01L45/1273 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.

Abstract translation: 本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。 绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。 底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。 顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

公开(公告)号：US08198619B2

公开(公告)日：2012-06-12

申请号：US12534599

申请日：2009-08-03

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen

IPC: H01L47/00

CPC classification number: H01L45/1273 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.

Abstract translation: 本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。 绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。 底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。 顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

公开(公告)号：US08094488B2

公开(公告)日：2012-01-10

申请号：US12965126

申请日：2010-12-10

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: G11C11/00

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。 该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。 该方法还包括确定存储器单元是处于较低电阻状态，以及如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。 第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。