Abstract:
A packet processing accelerator comprises a programmable packet classification module, a programmable flow control module, and a programmable packet header modification module. The programmable packet classification module is configured to receive a data packet and generate a start location of each protocol header of the data packet and a first index. The first index indicates classification of the data packet. The programmable flow control module is configured to generate a code of an output port and an action code according to the start location of each protocol header of the data packet and the first index. The programmable packet header modification module is configured to modify content of a plurality of protocol headers of the data packet according to the action code and to send the modified data packet to an output port according to the code of the output port.
Abstract:
An addressing device for transmitting satellite TV signal is electrically connected with a satellite down-converter and at least one STB installed at a subscriber end. When the subscriber activates the STB for playing satellite TV channel programs, the satellite down-converter receives satellite signals provide by a satellite system end and processes the satellite signals to generate baseband satellite TV signal for input into the addressing device. Next, the addressing device receives GPS signal indicating the position where it is installed and then addresses the GPS signal, further executing digital security processes to converting the area address into an address signal having the same transmission frequency as that of the baseband satellite TV signal. Finally, the address signal is mixed with the baseband satellite TV signal for output to the STB.
Abstract:
An object tracking method includes steps of obtaining multiple first classifications of pixels within a first focus frame in a first frame picture, wherein the first focus frame includes an object to be tracked and has a first rectangular frame in a second frame picture; performing a positioning process to obtain a second rectangular frame; and obtaining color features of pixels around the second rectangular frame sequentially and establishing multiple second classifications according to the color feature. The established second classifications are compared with the first classifications sequentially to obtain an approximation value, compared with a predetermined threshold. The second rectangular frame is progressively adjusted, so as to establish a second focus frame. By analyzing color features of the pixels of the object and with a classification manner, the efficacy of detecting a shape and size of the object so as to update information of the focus frame is achieved.
Abstract:
A vehicle window assembly includes a vehicle structure, a window panel and a light source. The vehicle structure defines a viewing aperture. The window panel is mounted to the vehicle structure and covers the viewing aperture. The window panel has a peripheral edge surrounding a first window surface and a second window surface opposite the first window surface. The first window surface includes an etched section. The light source is mounted to the vehicle structure adjacent to a portion of the peripheral edge of the window panel such that light from the light source is directed to the portion of the peripheral edge of the window panel. The light travels in a lateral direction through the window panel selectively illuminating the etched section.
Abstract:
The present invention discloses a control method of an adaptive hybrid density memory storage device suitable for locating a data to the storage device. The storage device includes a high density memory unit and a low density memory unit. The method is characterized in that the property of the data is determined by its length, and the data is written to the high density memory unit or the low density memory unit according to the property of the data and the relative wearing rate and the amount of data processed by the storage device.
Abstract:
A printed circuit board (PCB) testing system includes two gear groups, a pair of transmission belts and a driver. The pair of transmission belts geared onto and driven by the two gear groups is parallel and respectively perpendicular to the PCB transmission guideway so as to define a PCB accommodation space therebetween. Each transmission belt includes a plurality of projections. The two gear groups are rotated synchronously and inversely. During operation, the projections on the pair of transmission belts, facing the PCB accommodation space, move down, the projections move away from each other and to the bottom of the corresponding transmission belts, and a PCB supported by the pair of projections drops onto the PCB transmission guideway.
Abstract:
A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.
Abstract:
Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by applying electrical and/or thermal energy to the metal-oxide material.
Abstract:
A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.