公开(公告)号：US11675404B2

公开(公告)日：2023-06-13

申请号：US17319880

申请日：2021-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo Mori ,  Kazuki Fukuoka ,  Kenichi Shimada

IPC: G06F1/26 ,  G06F1/28

CPC classification number: G06F1/263 ,  G06F1/28

Abstract: A semiconductor device includes: a plurality of cores configured to receive power from a power supply; a plurality of power switch circuits provided for each core and configured to control the power supplied to the corresponding cores; a compare circuit configured to receive power from the power supply and compare output data of the plurality of cores; and a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply and the compare circuit.

公开(公告)号：US20230176883A1

公开(公告)日：2023-06-08

申请号：US17938475

申请日：2022-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi IGARASHI ,  Kenichi TAKEDA ,  Katsushige MATSUBARA ,  Tetsuya SHIBAYAMA

IPC: G06F9/455 ,  G06F9/4401

CPC classification number: G06F9/45541 ,  G06F9/4406

Abstract: According to one embodiment, a semiconductor device restricts an OS capable of using a functional block by an OS identifier written in an attribute register for restricting an accessible OS, and creates operation setting values of a first input unit, a second input unit, and a screen synthesis unit per OS to describe them in a setting value list stored in a shared memory, and each of the first input unit, second input unit, and screen synthesis unit has a mask circuit that refers to the OS identifier of the attribute register and in which write of the operation setting values into the setting register group of an own block is hampered, the operation setting values being described in the setting value list created by an OS other than the OS having a use authority for the own block.

公开(公告)号：US20230169167A1

公开(公告)日：2023-06-01

申请号：US17958775

申请日：2022-10-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MINAKI

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: A semiconductor device provides a method to avoid side-channel attacks. While the logic circuit A for performing the encryption process does not operate, by operating the logic circuit B (performing processing other than the encryption) having a circuit scale of approximately the same as the logic circuit A, the change in the consumption current interlocked with the operation state of the logic circuit A is shielded, it is possible to make it difficult to decrypt the encryption key of the logic circuit A by analyzing the current waveform.

公开(公告)号：US20230155013A1

公开(公告)日：2023-05-18

申请号：US17529863

申请日：2021-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L29/7396 ,  H01L27/0635 ,  H01L28/20

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of IGBTs (Insulated Gate Bipolar Transistors) formed on the semiconductor substrate), a gate electrode, a plurality of gate wires coupled to the gates of the IGBTs, and a gate resistor coupled to the gate electrode and the plurality of gate wires, wherein the gate resistor comprises a resistive element, a first contact that couples the gate electrode and the resistive element, and a plurality of second contacts each of which corresponds to each of the plurality of gate wires and couples to the resistive element and the corresponding gate wire, respectively, and wherein each of the plurality of second contacts is formed at a different distance from the first contact.

公开(公告)号：US20230145662A1

公开(公告)日：2023-05-11

申请号：US17965308

申请日：2022-10-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi TAKEDA ,  Takahiro SHIMOI ,  Masaya NAKANO ,  Hidenori MITANI ,  Yoshinobu KANEDA

IPC: H03F3/45

CPC classification number: H03F3/45744 ,  H03F3/45497 ,  H03F3/45511

Abstract: Speed enhancement of data reading is achieved while suppressing an influence of an offset voltage of a differential amplifier. The differential amplifier includes: a current source that is connected to a first power supply in which a suppliable current is a first current; an active element pair that is connected to the current source, and amplifies a signal input to an input terminal pair to output an output signal pair; a load element pair that is connected to a second power supply different in power supply voltage from the first power supply, the load element pair serving for outputting the output signal pair to an output terminal pair; and a capacitance element pair that is inserted between an external input terminal pair and the input terminal pair; a switching element pair that charges the capacitance element pair to generate a voltage, which is obtained by converting an offset voltage of the input terminal pair into an input voltage, in the capacitance element pair by short-circuiting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit that controls a current suppliable by the current source to a second current larger than the first current at a time of performing the charge.

公开(公告)号：US20230145455A1

公开(公告)日：2023-05-11

申请号：US17948769

申请日：2022-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Suguru FUJITA

IPC: B60W50/14 ,  B60W30/095 ,  B60W40/04 ,  H04W4/46

CPC classification number: B60W50/14 ,  B60W30/0956 ,  B60W40/04 ,  H04W4/46 ,  B60W2420/42 ,  B60W2420/52 ,  B60W2554/4046 ,  B60W2556/60 ,  B60W2556/65

Abstract: A collision-avoidance system includes a sensor, a surrounding monitoring system that outputs monitoring detection information based on information acquired by the sensor, an surrounding area information acquisition system that outputs surrounding area information related to a current location, and an assistance system that generates assistance information for controlling the surrounding monitoring system based on the surrounding area information and outputs the generated assistance information to the surrounding monitoring system.

公开(公告)号：US20230144840A1

公开(公告)日：2023-05-11

申请号：US17894572

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki SASAKI ,  Tatsuaki TSUKUDA ,  Hiroya SHIMOYAMA

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/481 ,  H01L23/49513 ,  H01L24/29 ,  H01L25/074 ,  H01L2224/29139

Abstract: A semiconductor device includes a semiconductor chip hazing a non-overlapping region in which a source pad for main transistor and a clip do not overlap with each other. At this time, a sense transistor is arranged in a region of the non-overlapping region, which is located between a first portion of the clip and a first short side of the source pad for main transistor in a plan view.

公开(公告)号：US20230111142A1

公开(公告)日：2023-04-13

申请号：US17886049

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Yuta NABUCHI ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.

公开(公告)号：US20230090409A1

公开(公告)日：2023-03-23

申请号：US17480007

申请日：2021-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eiji TSUKUDA ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric film, a conductive film, at least one ferroelectric film, a second dielectric film, a memory gate electrode, a third dielectric film and a control gate electrode. The semiconductor substrate includes a source region and a drain region. The semiconductor substrate includes a first region and a second region between the source region and the drain region. The first dielectric film is formed on the first region. The conductive film is formed on the first dielectric film. The at least one ferroelectric film is formed on one hart of the conductive film. The second dielectric film is formed on the other part of the conductive film. The memory gate electrode is formed on the ferroelectric film. The third dielectric film is formed on the second region. The control gate electrode is formed on the third dielectric film.

公开(公告)号：US20230088709A1

公开(公告)日：2023-03-23

申请号：US17879524

申请日：2022-08-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kouji SATOU ,  Shunya NAGATA ,  Jiro ISHIKAWA

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.