公开(公告)号：US20230134000A1

公开(公告)日：2023-05-04

申请号：US17887094

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki SEKIKAWA ,  Yasutaka NAKASHIBA ,  Hideki SASAKI ,  Hajime HAYASHIMOTO

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a clip which is electrically connected to a main-transistor source pad via a first silver paste and is connected to a lead via a second silver paste. The clip has a “first part” with which the first silver paste is in contact, a “second part” with which the second silver paste is in contact, and a “third part” positioned between the “first part” and the “second part”. A protruding member is formed on a surface of the main-transistor source pad, and the “first part” is in contact with the protruding member.

公开(公告)号：US20230144840A1

公开(公告)日：2023-05-11

申请号：US17894572

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki SASAKI ,  Tatsuaki TSUKUDA ,  Hiroya SHIMOYAMA

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/481 ,  H01L23/49513 ,  H01L24/29 ,  H01L25/074 ,  H01L2224/29139

Abstract: A semiconductor device includes a semiconductor chip hazing a non-overlapping region in which a source pad for main transistor and a clip do not overlap with each other. At this time, a sense transistor is arranged in a region of the non-overlapping region, which is located between a first portion of the clip and a first short side of the source pad for main transistor in a plan view.

公开(公告)号：US20160156231A1

公开(公告)日：2016-06-02

申请号：US14896867

申请日：2013-06-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki SHIBUYA ,  Hideki SASAKI ,  Tatsuaki TSUKUDA ,  Tadashi SHIMIZU ,  Masahiro DOBASHI ,  Shinji NISHIZONO ,  Hiroko KUBOTA

IPC: H02J50/12 ,  H04B5/00

CPC classification number: H02J50/12 ,  H02J7/025 ,  H02J50/80 ,  H04B5/0037 ,  H04B5/0081

Abstract: In a communication control device in which an antenna electrode having an antenna connected thereto, a power supply circuit, and a communication circuit are mounted on a mounting board, the antenna electrode is disposed at one corner portion on a principal surface of the mounting board, the communication circuit is disposed on a side of a first side of the principal surface that shares the corner portion, and the power supply circuit is disposed on a side of a second side facing the first side. Further, a first signal path connecting the antenna electrode and the communication circuit extends along the first side, and a second signal path connecting the antenna electrode and the power supply circuit extends along a third side that shares the corner portion and is perpendicular to the first side.

Abstract translation: 在其中连接有天线的天线电极，电源电路和通信电路安装在安装板上的通信控制装置中，天线电极设置在安装板的主表面上的一个角部， 通信电路设置在共享角部的主表面的第一侧的一侧，并且电源电路设置在面向第一侧的第二侧的一侧。 此外，连接天线电极和通信电路的第一信号路径沿着第一侧延伸，并且连接天线电极和电源电路的第二信号路径沿共享角部的第三侧延伸并垂直于第一 侧。

公开(公告)号：US20170207535A1

公开(公告)日：2017-07-20

申请号：US15324650

申请日：2014-07-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuaki TSUKUDA ,  Hideki SASAKI

IPC: H01Q7/00 ,  H01Q3/24 ,  H01Q1/24

CPC classification number: H01Q7/00 ,  H01Q1/24 ,  H01Q3/24 ,  H02J50/27 ,  H02J50/80

Abstract: A loop antenna 1 includes: a first electrode terminal 2c; a second electrode terminal 2d arranged to make a pair with the first electrode terminal 2c; and a loop-shaped member 2 which has one end connected to the first electrode terminal 2c and the other end connected to the second electrode terminal 2d, is wound a plurality of times, and is made of a conductive material. The first electrode terminal 2c and the second electrode terminal 2d are arranged so as to make a pair with respect to a center line 3 of the loop-shaped member 2. Further, the loop-shaped member 2 includes a first loop-shaped member 2a, a second loop-shaped member 2b, and an intersection part 2e. The intersection part 2e is arranged on the center line 3 in a plan view, and the loop-shaped member 2 is continuously connected and formed to be symmetrical with respect to the center line 3.

公开(公告)号：US20140167292A1

公开(公告)日：2014-06-19

申请号：US14105281

申请日：2013-12-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro MASUMURA ,  Hideki SASAKI ,  Toshiharu OKAMOTO

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01079 ,  H01L2224/4554

Abstract: The present invention provides a multichip package in which a first semiconductor chip having an RF analog circuit area and a digital circuit area, and a second semiconductor chip having a digital circuit area are plane-arranged over an organic multilayer wiring board and coupled to each other by bonding wires. In the multichip package, the first semiconductor chip is made thinner than the second semiconductor chip.

Abstract translation: 本发明提供一种多芯片封装，其中具有RF模拟电路区域和数字电路区域的第一半导体芯片以及具有数字电路区域的第二半导体芯片平面排列在有机多层布线板上并彼此耦合 通过接合线。 在多芯片封装中，使第一半导体芯片比第二半导体芯片薄。