公开(公告)号：US20230326922A1

公开(公告)日：2023-10-12

申请号：US18170153

申请日：2023-02-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroya SHIMOYAMA

IPC: H01L27/06 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L29/4236 ,  H01L27/0255

Abstract: A sense MOSFET is formed at a position surrounded by a main MOSFET and a source pad connected to a source region of the main MOSFET in plan view. A source potential is supplied to a source region of the sense MOSFET via a wiring surrounded by the source pad in plan view, a field plate electrode formed in a trench together with a gate electrode, and wirings formed outside the source pad.

公开(公告)号：US20190088577A1

公开(公告)日：2019-03-21

申请号：US16048284

申请日：2018-07-29

Applicant: Renesas Electronics Corporation

Inventor： Hiroya SHIMOYAMA ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H05K7/20

Abstract: Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. As viewed in a plane, the leads LD9 intersect with a side MRd4 of the sealing portion and the leads LD10 intersect with a side MRd2 of the sealing portion.

公开(公告)号：US20240170571A1

公开(公告)日：2024-05-23

申请号：US18516760

申请日：2023-11-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori HOSHINO ,  Hiroya SHIMOYAMA ,  Toshimune KANBARA ,  Masataka NOMURA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407

Abstract: A semiconductor device includes a vertical MOSFET in which a trench including a gate electrode and a field plate electrode therebelow at a gate potential and a trench including a gate electrode and a field plate electrode therebelow at a source potential are alternately arranged on an upper surface of a semiconductor substrate in a plan view.

公开(公告)号：US20180218969A1

公开(公告)日：2018-08-02

申请号：US15850009

申请日：2017-12-21

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki NAKAMURA ,  Hiroya SHIMOYAMA

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L27/06 ,  H01L29/66 ,  H02P27/06 ,  H02M7/00 ,  H02M7/537

CPC classification number: H01L23/49575 ,  B62D5/0406 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0655 ,  H01L27/0629 ,  H01L29/66992 ,  H01L29/78 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/09165 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/40499 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/49179 ,  H01L2224/49505 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83862 ,  H01L2224/84801 ,  H01L2224/84862 ,  H01L2224/85013 ,  H01L2224/92246 ,  H01L2224/92247 ,  H02M7/003 ,  H02M7/537 ,  H02P27/06 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/01047

Abstract: The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

公开(公告)号：US20240170548A1

公开(公告)日：2024-05-23

申请号：US18515187

申请日：2023-11-20

Applicant: Renesas Electronics Corporation

Inventor： Hiroya SHIMOYAMA

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7889

Abstract: Provided is a semiconductor device including a field plate electrode, a floating electrode, and a gate electrode and satisfying a relationship of T1>T2>T3, where T1 is a thickness of an insulating film between the field plate electrode and an N-type drift region, T2 is a thickness of the insulating film between the floating electrode and the N-type drift region, and T3 is a thickness of the insulating film between the gate electrode and a P-type channel region.

公开(公告)号：US20230144840A1

公开(公告)日：2023-05-11

申请号：US17894572

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki SASAKI ,  Tatsuaki TSUKUDA ,  Hiroya SHIMOYAMA

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/481 ,  H01L23/49513 ,  H01L24/29 ,  H01L25/074 ,  H01L2224/29139

Abstract: A semiconductor device includes a semiconductor chip hazing a non-overlapping region in which a source pad for main transistor and a clip do not overlap with each other. At this time, a sense transistor is arranged in a region of the non-overlapping region, which is located between a first portion of the clip and a first short side of the source pad for main transistor in a plan view.

公开(公告)号：US20210118781A1

公开(公告)日：2021-04-22

申请号：US17060545

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazunori HASEGAWA ,  Yuichi YATO ,  Hiroyuki NAKAMURA ,  Yukihiro SATO ,  Hiroya SHIMOYAMA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.