公开(公告)号：US09741622B2

公开(公告)日：2017-08-22

申请号：US14608902

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of insulating material, forming an initial strain relaxed buffer layer such that it only partially fills the replacement fin cavities, implanting carbon into the initial strain relaxed buffer layer in the NMOS region, forming a channel semiconductor material on the initial strain relaxed buffer layer within the replacement fin cavities in both the NMOS region and the PMOS region to thereby define an NMOS fin comprised of the channel semiconductor material and a carbon-doped strain relaxed buffer layer and a PMOS fin comprised of the channel semiconductor material and the initial strain relaxed buffer layer and forming gate structures for the NMOS and PMOS devices.

公开(公告)号：US09634123B2

公开(公告)日：2017-04-25

申请号：US14676909

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7854

Abstract: A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.

公开(公告)号：US09633947B2

公开(公告)日：2017-04-25

申请号：US14608337

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/20 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53276 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2221/1094

Abstract: A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material.

公开(公告)号：US09590040B2

公开(公告)日：2017-03-07

申请号：US14341000

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/84 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial fin structure above a semiconductor substrate, forming a layer of insulating material around the sacrificial fin structure, removing the sacrificial fin structure so as to define a replacement fin cavity in the layer of insulating material that exposes an upper surface of the substrate, forming a replacement fin in the replacement fin cavity on the exposed upper surface of the substrate, recessing the layer of insulating material, and forming a gate structure around at least a portion of the replacement fin exposed above the recessed layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲鳍结构，在牺牲鳍结构周围形成绝缘材料层，去除牺牲鳍结构，以便在 绝缘材料，其暴露衬底的上表面，在所述衬底的暴露的上表面上的替换翅片腔中形成替换翅片，使所述绝缘材料层凹陷，以及在所述替换鳍片的至少一部分周围形成栅极结构 暴露在绝缘材料的凹陷层上方。

公开(公告)号：US09478663B2

公开(公告)日：2016-10-25

申请号：US14526617

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Yi Qi ,  Sylvie Mignot

IPC: H01L21/336 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/18 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/324 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract translation: 一种方法包括在半导体衬底上形成翅片并在翅片的侧壁上形成凹槽。 凹槽中形成硅合金材料。 进行热处理以从硅合金材料和翅片限定硅合金翅片部分。 半导体器件包括衬底，限定在衬底上的翅片和邻近翅片设置的隔离结构。 在隔离结构上方延伸的翅片的第一部分具有基本上垂直的侧壁和不同于在隔离结构上方延伸的翅片的第二部分的不同材料组成。

公开(公告)号：US20160190339A1

公开(公告)日：2016-06-30

申请号：US15065998

申请日：2016-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ajey Poovannummoottil Jacob

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof. A second epi semiconductor material is positioned on the first epi semiconductor material, the second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of the sidewall spacer and having a second lateral width at an upper surface thereof that is greater than the first lateral width. A metal silicide region is positioned on the upper surface of the second epi semiconductor material.

Abstract translation: 半导体器件包括源极/漏极区域，栅极结构，位于栅极结构上方的栅极盖层和邻近栅极结构的相对侧定位的侧壁间隔物。 第一外延半导体材料位于源极/漏极区域中，第一外延半导体材料在其上表面具有第一横向宽度。 第二外延半导体材料定位在第一外延半导体材料上，第二外延半导体材料横向延伸并覆盖侧壁间隔物的最上端的至少一部分，并且在其上表面具有更大的第二横向宽度 比第一横向宽度。 金属硅化物区域位于第二外延半导体材料的上表面上。

公开(公告)号：US20160190323A1

公开(公告)日：2016-06-30

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

公开(公告)号：US09368591B2

公开(公告)日：2016-06-14

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L21/338 ,  H01L29/45

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20160163863A1

公开(公告)日：2016-06-09

申请号：US14560361

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/201 ,  H01L21/02 ,  H01L29/161 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括在翅片的整个轴向长度周围围绕翅片的暴露部分形成初始外延半导体包层材料，在其周围形成牺牲栅极结构 去除所述牺牲栅极结构从而限定替换栅极腔，通过所述替换栅极腔执行蚀刻工艺以移除所述初始包层材料的至少暴露部分，从而暴露出所述牺牲栅极结构 在替换栅极腔内的翅片的表面，在散热片的暴露表面周围形成至少一个替代外延半导体覆层材料，以及在所述替代栅极腔内形成围绕所述至少一个替代外延半导体包层材料的替代栅极结构。

公开(公告)号：US09362405B1

公开(公告)日：2016-06-07

申请号：US14560361

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括在翅片的整个轴向长度周围围绕翅片的暴露部分形成初始外延半导体包层材料，在其周围形成牺牲栅极结构 去除所述牺牲栅极结构从而限定替换栅极腔，通过所述替换栅极腔执行蚀刻工艺以移除所述初始包层材料的至少暴露部分，从而暴露出所述牺牲栅极结构 在替换栅极腔内的翅片的表面，在散热片的暴露表面周围形成至少一个替代外延半导体覆层材料，以及在所述替代栅极腔内形成围绕所述至少一个替代外延半导体包层材料的替代栅极结构。