公开(公告)号：US09099401B2

公开(公告)日：2015-08-04

申请号：US14028827

申请日：2013-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure.

Abstract translation: 半导体器件包括第一组和第二组平行翅片，每组散热片具有相同数量的翅片，并且相邻散热片之间的间距低于相关光刻工艺的最小间距，其中第一组和第二组翅片之间的间隔 大于相邻翅片之间的间距; 在第一和第二组翅片上的门结构; 合并源区域，其在所述栅极结构的第一侧上连接所述第一和第二组翅片; 以及在栅极结构的第二侧连接第一组翅片和第二组翅片的合流漏极区域。

公开(公告)号：US09059019B2

公开(公告)日：2015-06-16

申请号：US13954453

申请日：2013-07-30

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.

Abstract translation: 具有掺杂阱区的半导体器件包括形成在半导体器件的衬底部分上的掺杂衬底层。 掺杂衬底层沿着第一方向延伸以限定垂直于第一方向的长度和第二方向以限定宽度。 在掺杂衬底层上形成多个翅片，并且在每个鳍片之间形成氧化物衬底层。 至少一个栅极形成在氧化物衬底层上并延伸穿过多个翅片中的至少一个翅片。

公开(公告)号：US09054218B2

公开(公告)日：2015-06-09

申请号：US13961248

申请日：2013-08-07

Applicant: International Business Machines Corporation

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors.

Abstract translation: 一种用于制造鳍状场效应晶体管（FinFET）器件的方法包括：在衬底上形成多个翅片，在翅片之间外延生长牺牲外延区域，在外延形状的合并开始之间停止牺牲外延区域的生长 并且在包括散热片和牺牲外延区域的基板上形成电介质层，其中介电层的一部分位于从相邻晶体管的散热片延伸的牺牲外延区域之间。

公开(公告)号：US20150048430A1

公开(公告)日：2015-02-19

申请号：US14028827

申请日：2013-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/78

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure.

Abstract translation: 半导体器件包括第一组和第二组平行翅片，每组散热片具有相同数量的翅片，并且相邻散热片之间的间距低于相关光刻工艺的最小间距，其中第一和第二组翅片之间的间隔 大于相邻翅片之间的间距; 在第一和第二组翅片上的门结构; 合并源区域，其在所述栅极结构的第一侧上连接所述第一和第二组翅片; 以及在栅极结构的第二侧连接第一组翅片和第二组翅片的合流漏极区域。

公开(公告)号：US20150048429A1

公开(公告)日：2015-02-19

申请号：US13968807

申请日：2013-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/311 ,  H01L29/78

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers; forming a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching the top insulator layer; and etching the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned.

Abstract translation: 半导体器件和侧壁图像传输方法，在硬掩模上旋转。 用于形成翅片的方法包括通过包括顶部和底部绝缘体层的层叠层和在基底上待图案化的层形成沟槽; 各向同性蚀刻顶部和底部绝缘体层; 在所述沟槽中形成硬掩模材料至所述底部绝缘体层的水平面; 各向同性蚀刻顶部绝缘体层; 并且将底部绝缘体层和待图案化的层蚀刻到衬底上以从待图案化的层形成翅片。

公开(公告)号：US08957478B2

公开(公告)日：2015-02-17

申请号：US13925105

申请日：2013-06-24

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.

公开(公告)号：US10734385B2

公开(公告)日：2020-08-04

申请号：US16548265

申请日：2019-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L29/04 ,  H01L27/092 ,  H01L29/78 ,  H01L29/165 ,  H01L21/18 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

公开(公告)号：US10559662B2

公开(公告)日：2020-02-11

申请号：US15467821

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Hong He ,  Juntao Li

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/28 ,  H01L29/161 ,  H01L29/04

Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

公开(公告)号：US10529829B2

公开(公告)日：2020-01-07

申请号：US15445287

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L21/322 ,  H01L21/02 ,  H01L21/324

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

公开(公告)号：US20190172940A1

公开(公告)日：2019-06-06

申请号：US16267618

申请日：2019-02-05

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L29/78 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).