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222 条记录 (耗时 0.022 秒)

    Integrated high-performance decoupling capacitor and heat sink
    121.
    发明授权
    Integrated high-performance decoupling capacitor and heat sink 失效
    集成高性能去耦电容和散热片

    公开(公告)号：US06236103B1

    公开(公告)日：2001-05-22

    申请号：US09283828

    申请日：1999-03-31

    申请人： Kerry Bernstein ,  Robert M. Geffken ,  Wilbur D. Pricer ,  Anthony K. Stamper ,  Steven H. Voldman

    发明人： Kerry Bernstein ,  Robert M. Geffken ,  Wilbur D. Pricer ,  Anthony K. Stamper ,  Steven H. Voldman

    IPC分类号： H01L2900

    CPC分类号： H01L28/40 ,  H01L23/3672 ,  H01L23/3735 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

    摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

    摘要翻译： 一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。 这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物 导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。 去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。 因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

    Clocked buffer circuit
    122.
    发明授权
    Clocked buffer circuit 失效
    时钟缓冲电路

    公开(公告)号：US4727267A

    公开(公告)日：1988-02-23

    申请号：US062036

    申请日：1987-06-15

    申请人： Kerry Bernstein

    发明人： Kerry Bernstein

    IPC分类号： G11C7/00 ,  G11C8/16 ,  G11C8/18 ,  G11C8/20 ,  H03K19/094

    CPC分类号： G11C8/20 ,  G11C7/00 ,  G11C8/16 ,  G11C8/18

    摘要： The present invention is especially directed towards an improved clocked buffer circuit that will clock, decode, repeat and invert an input signal. The clocked buffer circuit uses a clocked latch coupled to a decode circuit such that not only will the applied clock signal control the decode circuit, but the output of the latch will also control the decode circuit thus assuring the output of the decode circuit becomes latched into the set by the input clock signal.

    摘要翻译： 本发明特别涉及一种改进的时钟缓冲电路，其将对输入信号进行时钟，解码，重复和反转。 时钟缓冲电路使用与解码电路耦合的时钟锁存器，使得所施加的时钟信号不仅控制解码电路，而且锁存器的输出也将控制解码电路，从而确保解码电路的输出被锁存 由输入时钟信号设定。

    BEOL compatible FET structrure
    123.
    发明授权
    BEOL compatible FET structrure 有权
    BEOL兼容FET结构

    公开(公告)号：US08569803B2

    公开(公告)日：2013-10-29

    申请号：US13572742

    申请日：2012-08-13

    申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

    发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

    IPC分类号： H01L29/76

    CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

    摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

    Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage
    125.
    发明授权
    Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage 有权
    基于可制造性，测试覆盖和可选地诊断覆盖的组合来设计集成电路的方法

    公开(公告)号：US08347260B2

    公开(公告)日：2013-01-01

    申请号：US12880228

    申请日：2010-09-13

    申请人： Kerry Bernstein ,  James A. Culp ,  Leah M. P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  James A. Culp ,  Leah M. P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

    IPC分类号： G06F11/22

    CPC分类号： G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

    摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

    摘要翻译： 披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。 根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。 或者，可以根据DFM修改建立集成电路的测试覆盖。 或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。 或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。 在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

    DEEP TRENCH ELECTROSTATIC DISCHARGE (ESD) PROTECT DIODE FOR SILICON-ON-INSULATOR (SOI) DEVICES
    128.
    发明申请
    DEEP TRENCH ELECTROSTATIC DISCHARGE (ESD) PROTECT DIODE FOR SILICON-ON-INSULATOR (SOI) DEVICES 失效
    用于硅绝缘体（SOI）器件的深度放电静电放电（ESD）保护二极管

    公开(公告)号：US20120083091A1

    公开(公告)日：2012-04-05

    申请号：US13324486

    申请日：2011-12-13

    申请人： John E. Barth, JR. ,  Kerry Bernstein

    发明人： John E. Barth, JR. ,  Kerry Bernstein

    IPC分类号： H01L21/02

    CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L23/535 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.

    摘要翻译： 半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区和第一极性类型的扩散区的掩埋绝缘体层的顶部上的有源半导体层， 第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽 设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

    Multicore processor having storage for core-specific operational data
    130.
    发明授权
    Multicore processor having storage for core-specific operational data 有权
    具有用于核心特定操作数据的存储的多核处理器

    公开(公告)号：US08055822B2

    公开(公告)日：2011-11-08

    申请号：US11842206

    申请日：2007-08-21

    申请人： Kerry Bernstein ,  Nazmul Habib ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Nazmul Habib ,  Norman J. Rohrer

    IPC分类号： G06F13/12 ,  G06F19/00

    CPC分类号： G06F9/3851 ,  G06F9/3891

    摘要： An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data processing system, where the method includes providing a multicore processor that contains a plurality of processor cores and a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency for each of the plurality of processor cores. The method further includes operating a scheduler coupled to an operating system and to the multicore processor, where the scheduler is operated to be responsive at least in part to information read from the memory to schedule the execution of threads to individual ones of the processor cores for a more optimal usage of energy.

    摘要翻译： 集成电路包括多个处理器核心和可读非易失性存储器，其存储表示多个处理器核心中的每一个的至少一个操作特性的信息。 还公开了一种操作数据处理系统的方法，其中所述方法包括提供包含多个处理器核心的多核处理器和存储在测试操作期间确定的信息的可读非易失性存储器，其指示至少 用于所述多个处理器核心中的每一个的最大工作频率。 所述方法还包括操作耦合到操作系统和多核处理器的调度器，其中调度器被操作以至少部分地响应于从存储器读取的信息，以调度到处理器核心中的各个处理器核心的线程的执行 更优化的能量使用。