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    Integrated Assemblies Having Void Regions Between Digit Lines and Conductive Structures, and Methods of Forming Integrated Assemblies
    121.
    发明申请
    Integrated Assemblies Having Void Regions Between Digit Lines and Conductive Structures, and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20210174840A1

    公开(公告)日：2021-06-10

    申请号：US16709030

    申请日：2019-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Naveen Kaushik ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey

    IPC: G11C5/06 ,  H01L27/108

    Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

    SEMICONDUCTOR STRUCTURE FORMATION
    122.
    发明申请
    SEMICONDUCTOR STRUCTURE FORMATION 有权

    公开(公告)号：US20210066307A1

    公开(公告)日：2021-03-04

    申请号：US16555565

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

    IPC: H01L27/108

    Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

    Memory cells and memory arrays
    123.
    发明授权
    Memory cells and memory arrays 有权

    公开(公告)号：US10854611B2

    公开(公告)日：2020-12-01

    申请号：US16412750

    申请日：2019-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

    IPC: H01L27/108 ,  H01L29/78 ,  H01L29/94 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L23/528 ,  H01L29/08

    Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

    Integrated structures and methods of forming vertically-stacked memory cells
    125.
    发明授权
    Integrated structures and methods of forming vertically-stacked memory cells 有权

    公开(公告)号：US10388668B2

    公开(公告)日：2019-08-20

    申请号：US16184907

    申请日：2018-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

    Memory cells and memory arrays
    126.
    发明授权
    Memory cells and memory arrays 有权

    公开(公告)号：US10319724B2

    公开(公告)日：2019-06-11

    申请号：US16033377

    申请日：2018-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

    IPC: H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L29/94 ,  H01L23/528 ,  H01L29/08

    Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
    130.
    发明申请
    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells 有权
    形成垂直堆积记忆单元的综合结构和方法

    公开(公告)号：US20170012053A1

    公开(公告)日：2017-01-12

    申请号：US15248968

    申请日：2016-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

    IPC: H01L27/115 ,  H01L21/28 ,  H01L21/02

    CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

    Abstract translation: 一些实施例包括具有交替介电水平和导电水平的叠层，导电水平内的垂直堆叠的存储单元，堆叠上的绝缘材料和绝缘材料上的选择栅极材料的集成结构。 开口延伸穿过选择栅材料，穿过绝缘材料，并通过交替的电介质层和导电层叠。 绝缘材料内的开口的第一区域沿着选择栅极材料内的开口的第二区域的横截面较宽，并且沿着横截面比在交替堆叠内的开口的第三区域更宽 介电水平和导电水平。 通道材料在开口内并且与绝缘材料，选择栅极材料和存储单元相邻。 一些实施例包括形成垂直堆叠的存储器单元的方法。

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