公开(公告)号：US20150212882A1

公开(公告)日：2015-07-30

申请号：US14681564

申请日：2015-04-08

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/44 ,  G06F11/108 ,  G06F2211/104 ,  G11C29/52

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract translation: 本公开包括用于物理页面，逻辑页面和码字对应的装置和方法。 许多方法包括将多个数据的逻辑页面的错误编码为码字的数量并将码字的数量写入存储器的多个物理页面。 数据的逻辑页数可以不同于存储器的物理页数。

公开(公告)号：US08898424B2

公开(公告)日：2014-11-25

申请号：US13859502

申请日：2013-04-09

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F12/1045 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1004 ,  G06F2212/7201 ,  Y02D10/13

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。

公开(公告)号：US20140317374A1

公开(公告)日：2014-10-23

申请号：US14255525

申请日：2014-04-17

Applicant: Micron Technology, Inc.

Inventor： Martin L. Culley ,  Troy A. Manning ,  Troy D. Larsen

IPC: G06F12/02 ,  G06F12/14 ,  G06F12/10

CPC classification number: G06F3/0665 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/04 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1408 ,  G06F12/1475 ,  G06F2212/7201 ,  G06F2212/7202 ,  Y02D10/13

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract translation: 本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置 的特定范围以外的。

公开(公告)号：US08787101B2

公开(公告)日：2014-07-22

申请号：US13959395

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

IPC: G11C29/04 ,  G11C29/18 ,  G06F12/10 ,  G06F12/08 ,  G06F12/02 ,  G11C29/00

CPC classification number: G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract translation: 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。 描述其他实施例。

公开(公告)号：US20130227247A1

公开(公告)日：2013-08-29

申请号：US13859502

申请日：2013-04-09

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

IPC: G06F12/10

CPC classification number: G06F12/1045 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1004 ,  G06F2212/7201 ,  Y02D10/13

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。

公开(公告)号：US20250037755A1

公开(公告)日：2025-01-30

申请号：US18763395

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Timothy P. Finkbeiner ,  Glen E. Hush ,  Troy A. Manning ,  Troy D. Larsen ,  Peter L. Brown

IPC: G11C11/4091 ,  G11C11/4093 ,  H03K19/20

Abstract: Methods and apparatuses related to using non-zero selection circuitry. For example, the non-zero selection circuitry can determine whether a first word received from a first group of sense amplifiers has at least one bit having a first binary value, such as a logical “1”. In response to the first word being determined to have at least one bit having the first binary value, the first word can be outputted from the non-zero selection circuitry and a second word can be prevented from being outputted (even if the second word is determined to have at least one bit having the first binary value) at least while the first word is being outputted.

公开(公告)号：US11954499B2

公开(公告)日：2024-04-09

申请号：US17885143

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F9/4403 ,  G06F9/3836 ,  G06F9/4406 ,  G06F12/0868 ,  G06F12/1054 ,  G06F13/1668 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US11514957B2

公开(公告)日：2022-11-29

申请号：US17063495

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Perry V. Lea ,  Troy A. Manning

IPC: G11C8/00 ,  G11C7/10 ,  H03K19/173 ,  G06F13/12 ,  G11C11/408 ,  G11C8/12 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

公开(公告)号：US11355178B2

公开(公告)日：2022-06-07

申请号：US16219644

申请日：2018-12-13

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C11/4091 ,  G11C29/42 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

公开(公告)号：US20210407615A1

公开(公告)日：2021-12-30

申请号：US16914927

申请日：2020-06-29

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Troy D. Larsen ,  Jonathan D. Harms ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/00 ,  G11C29/18

Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.