公开(公告)号：US11716841B2

公开(公告)日：2023-08-01

申请号：US17142804

申请日：2021-01-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Indra V. Chary

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11710710B2

公开(公告)日：2023-07-25

申请号：US17443616

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  John M. Meldrim ,  Lifang Xu

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/562 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2221/1063

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

公开(公告)号：US20230063178A1

公开(公告)日：2023-03-02

申请号：US17564633

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Matthew J. King ,  Jason Reece ,  Michael J. Gossman ,  Shruthi Kumara Vadivel ,  Martin J. Barclay ,  Lifang Xu ,  Joel D. Peterson ,  Matthew Park ,  Adam L. Olson ,  David A. Kewley ,  Xiaosong Zhang ,  Justin B. Dorhout ,  Zhen Feng Yow ,  Kah Sing Chooi ,  Tien Minh Quan Tran ,  Biow Hiem Ong

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

公开(公告)号：US20230010799A1

公开(公告)日：2023-01-12

申请号：US17373258

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Richard J. Hill ,  Indra V. Chary ,  Lars P. Heineck

IPC: H01L29/417 ,  H01L23/528 ,  H01L21/768 ,  H01L29/40

Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

公开(公告)号：US20220336705A1

公开(公告)日：2022-10-20

申请号：US17855593

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Scott D. Schellhammer ,  Shan Ming Mou ,  Michael J. Bernhardt

IPC: H01L33/38 ,  H01L31/0216 ,  H01L33/22 ,  H01L31/0236 ,  H01L33/42 ,  H01L33/58

Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

公开(公告)号：US11476266B2

公开(公告)日：2022-10-18

申请号：US16799543

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Nancy M. Lomeli ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C5/06 ,  G11C5/02

Abstract: A microelectronic device comprises a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulating structures, a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers, conductive contact structures on the steps of the staircase structure, support pillar structures laterally offset in at least a first direction from the conductive contact structures and extending through the stack structure, and bridge structures comprising an electrically insulating material extending vertically through at least a portion of the stack structure and between at least some adjacent support pillar structures of the support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220302148A1

公开(公告)日：2022-09-22

申请号：US17205954

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Kar Wui Thong ,  Harsh Narendrakumar Jain

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

公开(公告)号：US20220231031A1

公开(公告)日：2022-07-21

申请号：US17153740

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Shuangqiang Luo ,  Harsh Narendrakumar Jain ,  Nancy M. Lomeli ,  Christopher J. Larsen

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

公开(公告)号：US11342265B2

公开(公告)日：2022-05-24

申请号：US16702222

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L27/11529 ,  H01L27/11556

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US20220139779A1

公开(公告)日：2022-05-05

申请号：US17577031

申请日：2022-01-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11524

Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.