-
公开(公告)号：US20180006852A1
公开(公告)日：2018-01-04
申请号：US15652059
申请日：2017-07-17
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
IPC: H04L27/01 , H04L7/033 , H04L1/00 , H04W52/20 , H04L25/03 , H04L25/497 , H04W52/22 , H04L7/00 , H04L25/02
CPC classification number: H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
-
公开(公告)号：US20170338979A1
公开(公告)日：2017-11-23
申请号：US15670916
申请日：2017-08-07
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC classification number: H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
-
公开(公告)号：US20170324591A1
公开(公告)日：2017-11-09
申请号：US15490725
申请日：2017-04-18
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Vladimir M. Stojanovic , Fred F. Chen
CPC classification number: H04L25/03019 , H04B1/1081 , H04L7/0058 , H04L7/0087 , H04L7/0331 , H04L25/03025 , H04L25/03038 , H04L25/03057 , H04L25/03343 , H04L25/03885
Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
-
124.发明授权公开(公告)号：US09735792B2
公开(公告)日：2017-08-15
申请号：US14651571
申请日：2014-01-03
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Masum Hossain
CPC classification number: H03L7/24 , H03K3/0307 , H03K3/0315 , H03L1/00 , H03L7/06
Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.
-
公开(公告)号：US09735791B2
公开(公告)日：2017-08-15
申请号：US15130802
申请日：2016-04-15
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
CPC classification number: H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
-
Patent Agency Ranking
126.发明申请Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing 审中-公开具有时钟恢复电路和自适应采样和均衡器时序的接收器公开(公告)号：US20170054576A1
公开(公告)日：2017-02-23
申请号：US15259662
申请日：2016-09-08
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC classification number: H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。
-
公开(公告)号：US20160308693A1
公开(公告)日：2016-10-20
申请号：US15092435
申请日：2016-04-06
Applicant: Rambus Inc.
Inventor： Vladimir M. Stojanovic , Andrew C. Ho , Anthony Bessios , Bruno W. Garlepp , Grace Tsang , Mark A. Horowitz , Jared L. Zerbe , Jason C. Wei
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.
-
公开(公告)号：US09455825B2
公开(公告)日：2016-09-27
申请号：US14868721
申请日：2015-09-29
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC classification number: H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
-
129.发明授权公开(公告)号：US09425997B2
公开(公告)日：2016-08-23
申请号：US14734426
申请日：2015-06-09
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
CPC classification number: H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
-
公开(公告)号：US09407473B2
公开(公告)日：2016-08-02
申请号：US14683081
申请日：2015-04-09
Applicant: Rambus Inc.
Inventor： Vladimir M. Stojanovic , Andrew C. Ho , Anthony Bessios , Bruno W. Garlepp , Grace Tsang , Mark A. Horowitz , Jared L. Zerbe , Jason C. Wei
IPC: H04L25/03 , H04L25/06 , H04L25/497
CPC classification number: H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.
-
-
-
-
-
-
-
-
-
Search Results
186
records
(took 0.026 seconds)
