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    FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
    121.
    发明授权
    FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines 失效
    FPGA架构具有可编程字长和宽度的RAM块以及专用地址和数据线

    公开(公告)号：US5933023A

    公开(公告)日：1999-08-03

    申请号：US708247

    申请日：1996-09-03

    申请人： Steven P. Young

    发明人： Steven P. Young

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    摘要： A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. Thus, the logic blocks of the FPGA can use these routing lines to access portions of RAM. In one embodiment, dedicated address and data lines access the RAM blocks of the present invention and are connectable to routing lines in the interconnect structure. These lines allow RAM blocks and arrays of RAM blocks to be configured long, wide, or in between, and allow logic blocks to conveniently access RAM blocks in a remote part of the chip. Access to the RAM blocks is efficient in any RAM configuration. Bidirectional buffers or pass devices segment the address and data lines at each RAM block so that a selectable number of RAM blocks can operate together as a RAM. In another embodiment, dedicated data lines are programmably connectable in a staggered arrangement so that RAM blocks can be connected over a long distance without conflict between the RAM blocks.

    摘要翻译： 随机存取存储器块或RAM块与FPGA可配置逻辑块集成的结构。 访问可配置逻辑块的路由线路还访问RAM块中的地址，数据和控制线。 因此，FPGA的逻辑块可以使用这些路由线来访问RAM的部分。 在一个实施例中，专用地址和数据线访问本发明的RAM块并且可连接到互连结构中的路由线。 这些线路允许RAM块和RAM块阵列被配置为长，宽或中间，并允许逻辑块方便地访问芯片的远程部分中的RAM块。 任何RAM配置都可以访问RAM块。 双向缓冲器或通过器件在每个RAM块上划分地址和数据线，以便可选择数量的RAM块可以一起作为RAM一起工作。 在另一个实施例中，专用数据线可编程地以交错布置连接，使得RAM块可以在长距离上连接，而不会在RAM块之间发生冲突。

    FPGA interconnect structure with high-speed high fanout capability
    122.
    发明授权
    FPGA interconnect structure with high-speed high fanout capability 失效
    FPGA互连结构具有高速高扇出功能

    公开(公告)号：US5907248A

    公开(公告)日：1999-05-25

    申请号：US20369

    申请日：1998-02-09

    申请人： Trevor J. Bauer ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Steven P. Young

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177 ,  H03K7/38

    CPC分类号： H03K19/17796 ,  H03K19/1737 ,  H03K19/17704

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away. According to a second aspect of the invention, high fanout signals can be distributed to any tile in the array. A signal on a horizontal long line traverses a row of tiles, in which it makes contact with the logic block in each tile through hex lines and single-length lines. The horizontal single-length lines connected to some horizontal hex lines can programmably drive vertical long lines. Using these programmable connections, the signal on the horizontal long line bus is transferred to the vertical long lines. From the vertical long lines, a high-fanout signal is delivered to an array of tiles.

    摘要翻译： 本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。 连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径 和瓷砖有一段距离。 可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。 在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片之外，然后继续并连接到瓦片六瓦片。 在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。 根据本发明的第二方面，高扇出信号可以分布到阵列中的任何瓦片。 水平长线上的信号穿过一排瓦片，通过十六进制线和单条线与其接触每个瓦片中的逻辑块。 连接到一些水平六边形线的水平单线可以编程地驱动垂直的长线。 使用这些可编程连接，水平长线总线上的信号传输到垂直长线。 从垂直长线，高扇出信号被传送到一组瓦片。

    Six-input multiplexer wtih two gate levels and three memory cells
    123.
    发明授权
    Six-input multiplexer wtih two gate levels and three memory cells 失效
    六输入多路复用器，两个门级和三个存储单元

    公开(公告)号：US5744995A

    公开(公告)日：1998-04-28

    申请号：US635096

    申请日：1996-04-17

    申请人： Steven P. Young

    发明人： Steven P. Young

    IPC分类号： H03K17/693 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K17/693 ,  H03K19/1778

    摘要： A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals.

    摘要翻译： 公开了在从输入端口到输出端口的信号路径中仅使用两个晶体管的六输入多路复用器。 多路复用器使用未解码的控制信号。 多路复用器使用三个控制信号，并要求不使用控制信号组合000和111。 其他六个控制信号组合001,010,011,100,101和110可以用于通过仅在信号路径中放置两个晶体管来选择六个输入信号，利用三个控制信号中的两个是 相同和第三个不同于其他两个。 当两个多路复用器使用公共输入信号时，会产生紧凑的布局。

    Multiplier circuits with optional shift function
    124.
    发明授权
    Multiplier circuits with optional shift function 有权
    具有可选移位功能的乘法电路

    公开(公告)号：US08706793B1

    公开(公告)日：2014-04-22

    申请号：US12417010

    申请日：2009-04-02

    申请人： Steven P. Young

    发明人： Steven P. Young

    IPC分类号： G06F7/52 ,  G06F7/53

    CPC分类号： G06F7/5324 ,  G06F5/01 ,  G06F7/53

    摘要： Multiplier circuits that can optionally be configured as bit shifters. An exemplary multiplier includes a one-hot circuit, a multi-bit multiplexing circuit, and a multiply block. The one-hot circuit has a multi-bit input and a multi-bit output. The multiplexing circuit has first and second multi-bit inputs and a multi-bit output, with the first input of the multiplexing circuit being coupled to the output of the one-hot circuit. The multiply block has first and second multi-bit inputs and a multi-bit output, with the first input of the multiply block being coupled to the output of the multiplexing circuit. When selected by the multiplexer, the position of the single high bit in the one-hot circuit output determines the number of bits by which the multiplier output is shifted relative to the second multiplier input. When the one-hot circuit output is not selected as an input to the multiplier, the multiplier performs a multiply function.

    摘要翻译： 可以选择配置为位移器的乘法器电路。 示例性乘法器包括单热电路，多位复用电路和乘法器。 单热电路具有多位输入和多位输出。 复用电路具有第一和第二多位输入和多位输出，多路复用电路的第一输入端耦合到单热电路的输出端。 乘法块具有第一和第二多位输入和多位输出，乘法器的第一输入端耦合到多路复用电路的输出端。 当由多路复用器选择时，单热电路输出中的单个高位的位置确定乘法器输出相对于第二乘法器输入移位的位数。 当单热输出未被选择为乘法器的输入时，乘法器执行乘法函数。

    HYDRAULIC WHEEL SUSPENSION SYSTEM FOR A 3-WHEELED MOTORCYCLE
    126.
    发明申请
    HYDRAULIC WHEEL SUSPENSION SYSTEM FOR A 3-WHEELED MOTORCYCLE 有权
    用于三轮摩托车的液压车轮悬挂系统

    公开(公告)号：US20130211674A1

    公开(公告)日：2013-08-15

    申请号：US13723702

    申请日：2012-12-21

    申请人： Steven P. Young

    发明人： Steven P. Young

    IPC分类号： B60G13/08

    CPC分类号： B62K5/027 ,  B60G13/08 ,  B60G17/0162 ,  B60G21/073 ,  B60G2300/122 ,  B60G2300/45 ,  B60K17/356 ,  B60W2300/156 ,  B60W2510/20 ,  B60Y2200/223 ,  B62J15/02 ,  B62J17/00 ,  B62K5/10

    摘要： A wheel suspension system for a three-wheeled motorcycle or “trike” includes parallel wheels mounted on vertically pivoting suspension arms governed by hydraulic pistons. The pistons have upper liquid reservoirs that are interconnected through a valve system, which interconnects the upper reservoirs when the trike is in motion, allowing opposing vertical wheel movements when banking through turns, and prevents liquid exchange when the trike is stopped, thereby holding the motorcycle upright, Embodiments include a manual and/or automatic valve control. A threshold switching speed for an automatic controller can be factory set and/or user adjustable. The pistons can include directly interconnected lower fluid reservoirs. A shock-absorbing reservoir can allow transient vertical movement of both wheels to absorb shocks. A cover system can emulate the appearance of saddle bags and can appear to be covering only a single wheel.

    摘要翻译： 用于三轮摩托车或“三轮车”的车轮悬挂系统包括安装在由液压活塞控制的垂直枢转悬挂臂上的平行轮。 活塞具有通过阀系统相互连接的上部液体储存器，当三通阀运动时，将上部储存器互连，允许相反的垂直车轮运动，当车辆转弯时，可防止三轮车停止时进行液体交换，从而保持摩托车 实施例包括手动和/或自动阀控制。 自动控制器的阈值切换速度可以在出厂设置和/或用户可调。 活塞可以包括直接互连的下部流体储存器。 减震水箱可以允许两个轮子的瞬时垂直运动以吸收冲击。 盖系统可以模拟鞍形袋的外观，并且似乎只能覆盖一个车轮。

    Error checking parity and syndrome of a block of data with relocated parity bits
    128.
    发明授权
    Error checking parity and syndrome of a block of data with relocated parity bits 有权
    错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验

    公开(公告)号：US08245102B1

    公开(公告)日：2012-08-14

    申请号：US12188939

    申请日：2008-08-08

    申请人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

    发明人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

    IPC分类号： G06F11/00

    CPC分类号： H03M13/27 ,  H03M13/19 ,  H03M13/45

    摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

    摘要翻译： 描述了用于错误检查信息的方法和装置。 配置数据包括数据位和奇偶校验位。 值得注意的是，可以重新定位奇偶校验位以确定校正子值。 通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。 识别配置数据的每个单词的位置。 确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。 存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。

    Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies
    130.
    发明授权
    Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
    在多产品可编程IC芯片的可选边界实现和建模互连线路的方法

    公开(公告)号：US08001511B1

    公开(公告)日：2011-08-16

    申请号：US12245858

    申请日：2008-10-06

    申请人： Trevor J. Bauer ,  Jeffrey V. Lindholm ,  F. Erich Goetting ,  Bruce E. Talley ,  Ramakrishna K. Tanikella ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Jeffrey V. Lindholm ,  F. Erich Goetting ,  Bruce E. Talley ,  Ramakrishna K. Tanikella ,  Steven P. Young

    IPC分类号： G06F17/50 ,  G01R31/28

    CPC分类号： H03K19/177 ,  G06F17/5054 ,  G06F17/5068

    摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.

    摘要翻译： 使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。 第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。 在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。 第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。 延伸到第二管芯边缘的互连线成对连接在一起。 两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。