公开(公告)号：US08913457B2

公开(公告)日：2014-12-16

申请号：US14271165

申请日：2014-05-06

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, SA

Inventor： Nishu Kohli ,  Robin M. Wilson

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘可操作的存储器组件。 存储电路还包括响应系统时钟产生内部时钟的内部时钟产生电路。 响应于系统时钟的上升沿和下降沿都产生内部时钟的第一个边沿。

公开(公告)号：US08908399B2

公开(公告)日：2014-12-09

申请号：US12782098

申请日：2010-05-18

Applicant: Stéphane Gamet ,  Joël Damiens

Inventor： Stéphane Gamet ,  Joël Damiens

IPC: H02M3/07

CPC classification number: H02M3/07

Abstract: A regulation device may be configured for regulating an output voltage of a charge pump voltage generator. The regulation device may include a first regulation loop capable of generating and delivering, to a first input of the voltage generator, an input voltage depending on the difference between the output voltage and a first reference voltage. The regulating device may also include a charger capable of generating and delivering, to a second input of the voltage generator, a substantially constant charge voltage. An electronic device may include the regulation device.

Abstract translation: 调节装置可以被配置用于调节电荷泵电压发生器的输出电压。 调节装置可以包括能够根据输出电压和第一参考电压之间的差产生并向电压发生器的第一输入传送输入电压的第一调节回路。 调节装置还可以包括能够产生并向电压发生器的第二输入端传送基本上恒定的充电电压的充电器。 电子设备可以包括调节装置。

公开(公告)号：US20140354276A1

公开(公告)日：2014-12-04

申请号：US14286431

申请日：2014-05-23

Applicant: STMicroelectronics SA

Inventor： Severin Trochut ,  Eric Remond

IPC: G01R33/07 ,  H01L43/06 ,  H01L43/04

CPC classification number: G01R33/072 ,  H01L43/04 ,  H01L43/065

Abstract: The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.

Abstract translation: 集成的霍尔效应传感器的半导体膜内的霍尔电压的产生在受到磁场时使用半导体膜内的电流的流动。 膜被设置在绝缘层的顶部，被称为掩埋层，其本身设置在包含位于绝缘层下方的掩埋电极的载体衬底的顶部上。 偏置电压施加到埋入电极。

公开(公告)号：US08901692B2

公开(公告)日：2014-12-02

申请号：US13316938

申请日：2011-12-12

Applicant: David Coulon ,  Benoit Deschamps ,  Frédéric Barbier

Inventor： David Coulon ,  Benoit Deschamps ,  Frédéric Barbier

IPC: H01L27/14 ,  H01L27/146

CPC classification number: H04N5/345 ,  H01L27/14605 ,  H01L27/14647 ,  H01L27/14689 ,  H04N5/378

Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.

Abstract translation: 成像装置包括在半导体衬底中形成的至少一个光电子，并装配有用于过滤至少一个不需要的辐射的过滤装置。 过滤装置以取决于不需要的辐射的波长的深度埋在半导体衬底中。

公开(公告)号：US20140341498A1

公开(公告)日：2014-11-20

申请号：US14271641

申请日：2014-05-07

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER

IPC: G02F1/225 ,  G02F1/015 ,  G02F1/025 ,  H01L31/18

CPC classification number: G02F1/025 ,  G02B2006/12142 ,  G02F1/0123 ,  G02F1/2257 ,  G02F2001/212

Abstract: A semiconductor electro-optical phase shifter may include a first optical action zone having a minimum doping level, a first lateral zone and a central zone flanking the first optical action zone along a first axis, doped respectively at first and second conductivity types so as to form a P-I-N junction between the first lateral zone and the central zone. The phase shifter may include a second optical action zone having a threshold doping level, and a second lateral zone flanking the second optical action zone with the central zone along the first axis doped at the first conductivity type so as to form a P-I-N junction between the second lateral zone and the central zone.

Abstract translation: 半导体电光移相器可以包括分别以第一和第二导电类型掺杂的具有最小掺杂水平的第一光学作用区域，第一横向区域和沿着第一轴线的第一光学作用区域的侧面的中心区域，以便 在第一侧向区域和中心区域之间形成PIN结。 移相器可以包括具有阈值掺杂水平的第二光学作用区域和位于第二光学作用区域的第二侧向区域，其中中心区域沿着以第一导电类型掺杂的第一轴线形成PIN结， 第二横向区域和中心区域。

公开(公告)号：US08849841B2

公开(公告)日：2014-09-30

申请号：US11533543

申请日：2006-09-20

Applicant: David Furodet ,  Nicolas Albarel

Inventor： David Furodet ,  Nicolas Albarel

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/30985

Abstract: A memory circuit for an Aho-Corasick type character recognition automaton uses a node tree for recognizing predetermined strings of characters in an incoming data stream. The recognization is based upon successive transitions in the node tree stored in memory in which each node corresponds to a recognized sequence of a character string. At least part of the nodes are related to a consecutive node by a valid transition, from an initial state to terminal states, with each one corresponding to a recognized character string This memory circuit includes first sets of consecutive memory addresses defining respectively strings of consecutive nodes accessible sequentially during successive transitions to a terminal state, and second sets of memory addresses defining multiple nodes each pointing to several states.

Abstract translation: 用于Aho-Corasick型字符识别自动机的存储器电路使用节点树来识别输入数据流中的预定字符串。 识别基于存储在存储器中的节点树中的连续转换，其中每个节点对应于识别的字符串的序列。 至少部分节点通过从初始状态到终端状态的有效转换与连续节点相关联，其中每一个对应于识别的字符串。该存储器电路包括分别定义连续节点序列的第一组连续存储器地址 在连续过渡到终端状态期间可顺序访问，以及定义多个节点的第二组存储器地址，每个指向多个状态。

公开(公告)号：US08843087B2

公开(公告)日：2014-09-23

申请号：US13355034

申请日：2012-01-20

Applicant: Baudouin Martineau ,  Olivier Richard ,  Frédérìc Gianesello

Inventor： Baudouin Martineau ,  Olivier Richard ,  Frédérìc Gianesello

IPC: H04B1/04 ,  H01Q25/00 ,  H03F3/60 ,  H01P5/16 ,  H03F3/195 ,  H01P5/12 ,  H01Q3/40

CPC classification number: H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/195 ,  H03F3/602 ,  H03F2200/411

Abstract: A multichannel combiner formed from 2 to 1 combiners, wherein: a first input channel of each 2 to 1 combiner is connected to the output of a settable-gain amplifier of a signal to be combined; all 2 to 1 combiners are electrically connected in series; and an output of a first 2 to 1 combiner defines an output of the multichannel combiner.

Abstract translation: 由2到1组合器形成的多通道组合器，其中：每个2至1个组合器的第一输入通道连接到要组合的信号的可设置增益放大器的输出; 所有2对1组合器串联电连接; 并且第一2到1组合器的输出定义多通道组合器的输出。

公开(公告)号：US08828797B2

公开(公告)日：2014-09-09

申请号：US13222317

申请日：2011-08-31

Applicant: Perceval Coudrain ,  Yacine Felk ,  Patrick Lamontagne

Inventor： Perceval Coudrain ,  Yacine Felk ,  Patrick Lamontagne

IPC: H01L21/77 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/92 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05687 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2224/80895 ,  H01L2924/00

Abstract: A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Abstract translation: 通过将至少两个部件组装在一起来制造三维一体化结构，其中每个部分包含覆盖有覆盖区域并具有自由侧的至少一个金属线。 在每个部分的覆盖区域中形成空腔，该空腔在金属线上开口。 两个部分连接在一起，自由面彼此面对，并且每个覆盖区域中的空腔彼此对准。 然后金属线通过在至少一个金属线路中的金属的电迁移彼此电连接，电解材料填充对准的空腔。

公开(公告)号：US08791401B2

公开(公告)日：2014-07-29

申请号：US13484417

申请日：2012-05-31

Applicant: Frederic Barbier ,  Frederic Lalanne

Inventor： Frederic Barbier ,  Frederic Lalanne

IPC: H01L27/148

CPC classification number: H04N5/37457 ,  H04N5/335 ,  H04N5/35554

Abstract: A method for controlling a pixel may include first and second photosites, each having a photodiode and a charge-transfer transistor, a read node, and an electronic read element, all of which are common to all the photosites. The method may include an accumulation of photogenerated charges in the photodiode of the first photosite during a first period, an accumulation of photogenerated charges in the photodiode of the second photosite during a second period shorter than the first period, a selection of the signal corresponding to the quantity of charges accumulated in the photodiode of a photosite having the highest unsaturated intensity or else a saturation signal, and a digitization of the selected signal.

Abstract translation: 用于控制像素的方法可以包括第一和第二光电子，每个具有光电二极管和电荷传输晶体管，读节点和电子读取元件，所有这些都是所有光电子所共有的。 所述方法可以包括在第一周期期间在第一光电二极管中的光生电荷的累积，在比第一周期短的第二周期期间光生电荷在第二光电二极管中的累积，对应于 积分在具有最高不饱和强度或饱和信号的光电二极管中的电荷量以及所选信号的数字化。

公开(公告)号：US20140197448A1

公开(公告)日：2014-07-17

申请号：US14155891

申请日：2014-01-15

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H01L27/02 ,  H01L21/8249

CPC classification number: H01L21/8249 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/747 ,  H01L29/87

Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.

Abstract translation: 在给定的CMOS技术中在体半导体衬底上制造集成电路，并且包括用于防止静电放电的半导体器件。 半导体器件具有并联和头对尾耦合的双栅极晶闸管。 每个晶闸管都有一对电极区域。 两个晶闸管分别具有两个单独的栅极和公共半导体栅极区域。 每个晶闸管的两个晶体管的电流增益的乘积大于1.至少一个晶闸管的每个电极区域具有垂直于相应对的两个电极的间隔方向测量的尺寸，该尺寸被调整 以便使可控硅的本征触发电压小于要保护的晶体管的击穿电压，并且在CMOS技术中产生。