公开(公告)号：US20200091190A1

公开(公告)日：2020-03-19

申请号：US16694756

申请日：2019-11-25

申请人： TOSHIBA MEMORY CORPORATION

发明人： Tomoo Hishida ,  Yoshihisa Iwata

IPC分类号： H01L27/11582 ,  G11C5/06 ,  G11C8/12 ,  G11C16/04 ,  G11C7/18 ,  G11C5/02 ,  H01L27/10 ,  H01L23/528 ,  H01L27/11575 ,  H01L29/792 ,  H01L27/11568

摘要： A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

公开(公告)号：US20200091164A1

公开(公告)日：2020-03-19

申请号：US16149093

申请日：2018-10-01

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Jun Liu

IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11531

摘要： Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device.

公开(公告)号：US20200083244A1

公开(公告)日：2020-03-12

申请号：US16685130

申请日：2019-11-15

申请人： UNITED MICROELECTRONICS CORP.

发明人： Wen-Chung CHANG ,  Tzu-Ping CHEN

IPC分类号： H01L27/11573 ,  H01L27/11568 ,  H01L27/11575

摘要： A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

公开(公告)号：US10586806B2

公开(公告)日：2020-03-10

申请号：US16047811

申请日：2018-07-27

申请人： TOSHIBA MEMORY CORPORATION

发明人： Tomoo Hishida ,  Yoshihisa Iwata

IPC分类号： G11C16/04 ,  H01L27/11582 ,  G11C5/06 ,  G11C8/12 ,  G11C7/18 ,  G11C5/02 ,  H01L27/10 ,  H01L23/528 ,  H01L27/11575 ,  H01L29/792 ,  H01L27/11568 ,  G11C5/04

摘要： A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

公开(公告)号：US20200066753A1

公开(公告)日：2020-02-27

申请号：US16667786

申请日：2019-10-29

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/51 ,  H01L21/768 ,  H01L23/535 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11575

摘要： A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source line formed over a substrate. The semiconductor device may include a channel pattern including a connection part disposed over the source line, and pillar parts protruding from the connection part in a first direction. The semiconductor device may include a well structure protruding from the connection part in the first direction and spaced apart from the source line. The semiconductor device may include a source contact structure protruding from the source line in the first direction and passing through the connection part. The semiconductor device may include a gate stack disposed between the source contact structure and the well structure and enclosing the pillar parts over the connection part.

公开(公告)号：US20200058671A1

公开(公告)日：2020-02-20

申请号：US16270570

申请日：2019-02-07

申请人： Samsung Electronics Co., Ltd.

发明人： Jun Hyoung KIM ,  Kwang Soo KIM ,  Seok Cheon BAEK ,  Geun Won LIM

IPC分类号： H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

摘要： A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

公开(公告)号：US10553605B2

公开(公告)日：2020-02-04

申请号：US15933695

申请日：2018-03-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji Mo Gu ,  Kyeong Jin Park ,  Hyun Mog Park ,  Byoung Il Lee ,  Tak Lee ,  Jun Ho Cha

IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565

摘要： A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

公开(公告)号：US10515977B2

公开(公告)日：2019-12-24

申请号：US16033357

申请日：2018-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Cheng Wu ,  Chien-Hung Chang

IPC分类号： H01L27/11575 ,  H01L29/06

摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a logic region having a plurality of transistor devices disposed within a substrate, an embedded memory region having a plurality of memory devices disposed within the substrate, and a boundary region separating the logic region from the embedded memory region. The boundary region includes a first isolation structure having a first upper surface and a second upper surface below the first upper surface. The first and second upper surfaces are coupled by an interior sidewall overlying the first isolation structure. The boundary region further includes a memory wall arranged on the second upper surface and surrounding the embedded memory region, and a logic wall arranged on the first upper surface and surrounding the memory wall. The logic wall has an upper surface that is above the plurality of memory devices and the memory wall.

公开(公告)号：US10515976B2

公开(公告)日：2019-12-24

申请号：US15885878

申请日：2018-02-01

申请人： UNITED MICROELECTRONICS CORP.

发明人： Wen-Chung Chang ,  Tzu-Ping Chen

IPC分类号： H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/51 ,  H01L21/28

摘要： A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

公开(公告)号：US10483282B2

公开(公告)日：2019-11-19

申请号：US16267151

申请日：2019-02-04

申请人： Applied Materials, Inc.

发明人： Michael Wenyoung Tsiang ,  Praket P. Jha ,  Xinhai Han ,  Bok Hoen Kim ,  Sang Hyuk Kim ,  Myung Hun Ju ,  Hyung Jin Park ,  Ryeun Kwan Kim ,  Jin Chul Son ,  Saiprasanna Gnanavelu ,  Mayur G. Kulkarni ,  Sanjeev Baluja ,  Majid K. Shahreza ,  Jason K. Foster

IPC分类号： H01L21/02 ,  C23C16/02 ,  C23C16/505 ,  C23C16/52 ,  C23C16/40 ,  H01L27/11582 ,  H01L29/06 ,  H01L21/3115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/768 ,  C23C16/455 ,  H01L21/311 ,  H01L21/3105

摘要： Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.