公开(公告)号：US11365476B2

公开(公告)日：2022-06-21

申请号：US16269337

申请日：2019-02-06

Applicant: Applied Materials, Inc.

Inventor： Praket P. Jha ,  Allen Ko ,  Xinhai Han ,  Thomas Jongwan Kwon ,  Bok Hoen Kim ,  Byung Ho Kil ,  Ryeun Kim ,  Sang Hyuk Kim

IPC: H01L27/11556 ,  C23C16/34 ,  H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/311 ,  H01L27/11582

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

公开(公告)号：US11060189B2

公开(公告)日：2021-07-13

申请号：US16464892

申请日：2017-12-18

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung Tsiang ,  Praket P. Jha ,  Deenesh Padhi

IPC: H01L21/02 ,  C23C16/44 ,  C23C16/24 ,  C23C16/40 ,  C23C16/505 ,  H01J37/32

Abstract: Implementations of the present disclosure provide methods for processing substrates in a processing chamber. In one implementation, the method includes (a) depositing a dielectric layer on a first substrate at a first chamber pressure using a first high-frequency RF power, (b) depositing sequentially a dielectric layer on N substrates subsequent to the first substrate at a second chamber pressure, wherein N is an integral number of 5 to 10, and wherein depositing each substrate of N substrates comprises using a second high-frequency RF power that has a power density of about 0.21 W/cm2 to about 0.35 W/cm2 lower than that of the first high-frequency RF power, (c) performing a chamber cleaning process without the presence of a substrate, and (d) repeating (a) to (c).

公开(公告)号：US11170994B1

公开(公告)日：2021-11-09

申请号：US17147454

申请日：2021-01-12

Applicant: Applied Materials, Inc.

Inventor： Jung Chan Lee ,  Praket P. Jha ,  Jingmei Liang ,  Jinrui Guo ,  Wenhui Li

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of depositing a silicon-containing material is disclosed. Some embodiments of the disclosure provide films which fill narrow CD features without a seam or void. Some embodiments of the disclosure provide films which form conformally on features with wider CD. Embodiments of the disclosure also provide superior quality films with low roughness, low defects and advantageously low deposition rates.

公开(公告)号：US10707116B2

公开(公告)日：2020-07-07

申请号：US15977380

申请日：2018-05-11

Applicant: Applied Materials, Inc.

Inventor： Jingmei Liang ,  Yong Sun ,  Jinrui Guo ,  Praket P. Jha ,  Jung Chan Lee ,  Tza-Jing Gung ,  Mukund Srinivasan

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/67 ,  C23C16/32 ,  C23C16/36 ,  C23C16/40 ,  H01J37/32 ,  C23C16/455 ,  C23C16/30 ,  C23C16/34 ,  C23C16/505 ,  C23C16/04

Abstract: Implementations disclosed herein relate to methods for forming and filling trenches in a substrate with a flowable dielectric material. In one implementation, the method includes subjecting a substrate having at least one trench to a deposition process to form a flowable layer over a bottom surface and sidewall surfaces of the trench in a bottom-up fashion until the flowable layer reaches a predetermined deposition thickness, subjecting the flowable layer to a first curing process, the first curing process being a UV curing process, subjecting the UV cured flowable layer to a second curing process, the second curing process being a plasma or plasma-assisted process, and performing sequentially and repeatedly the deposition process, the first curing process, and the second curing process until the plasma cured flowable layer fills the trench and reaches a predetermined height over a top surface of the trench.

公开(公告)号：US10483282B2

公开(公告)日：2019-11-19

申请号：US16267151

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung Tsiang ,  Praket P. Jha ,  Xinhai Han ,  Bok Hoen Kim ,  Sang Hyuk Kim ,  Myung Hun Ju ,  Hyung Jin Park ,  Ryeun Kwan Kim ,  Jin Chul Son ,  Saiprasanna Gnanavelu ,  Mayur G. Kulkarni ,  Sanjeev Baluja ,  Majid K. Shahreza ,  Jason K. Foster

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/505 ,  C23C16/52 ,  C23C16/40 ,  H01L27/11582 ,  H01L29/06 ,  H01L21/3115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/768 ,  C23C16/455 ,  H01L21/311 ,  H01L21/3105

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

公开(公告)号：US10410872B2

公开(公告)日：2019-09-10

申请号：US15695269

申请日：2017-09-05

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Ziqing Duan ,  Milind Gadre ,  Praket P. Jha ,  Abhijit Basu Mallick ,  Deenesh Padhi

IPC: H01L21/285 ,  C23C16/30 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3205 ,  C23C16/04 ,  C23C16/24 ,  H01L21/033

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a boron-doped amorphous silicon layer on the patterned features and the exposed upper surface of the substrate and selectively removing the boron-doped amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the boron-doped amorphous silicon layer.

公开(公告)号：US09837265B2

公开(公告)日：2017-12-05

申请号：US15192732

申请日：2016-06-24

Applicant: Applied Materials, Inc.

Inventor： Prashant Kumar Kulshreshtha ,  Sudha Rathi ,  Praket P. Jha ,  Saptarshi Basu ,  Kwangduk Douglas Lee ,  Martin J. Seamons ,  Bok Hoen Kim ,  Ganesh Balasubramanian ,  Ziqing Duan ,  Lei Jing ,  Mandar B. Pandit

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  H01L21/033 ,  H01L21/66 ,  C23C16/26 ,  C23C16/04 ,  H01L21/311

CPC classification number: H01L21/02274 ,  C23C16/04 ,  C23C16/26 ,  C23C16/455 ,  C23C16/45502 ,  C23C16/45508 ,  C23C16/45565 ,  C23C16/458 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/46 ,  H01L21/02115 ,  H01L21/0337 ,  H01L21/31144 ,  H01L22/12

Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.

公开(公告)号：US20220375747A1

公开(公告)日：2022-11-24

申请号：US17325764

申请日：2021-05-20

Applicant: Applied Materials, Inc.

Inventor： Wenhui Li ,  Praket P. Jha ,  Mandar B. Pandit ,  Man-Ping Cai ,  Jingmei Liang ,  Michael Wenyoung Tsiang

IPC: H01L21/02

Abstract: Processing methods disclosed herein comprise forming a nucleation layer and a flowable chemical vapor deposition (FCVD) film on a substrate surface by exposing the substrate surface to a silicon-containing precursor and a reactant. By controlling at least one of a precursor/reactant pressure ratio, a precursor/reactant flow ratio and substrate temperature formation of miniature defects is minimized. Controlling at least one of the process parameters may reduce the number of miniature defects. The FCVD film can be cured by any suitable curing process to form a smooth FCVD film.

公开(公告)号：US11367614B2

公开(公告)日：2022-06-21

申请号：US16929357

申请日：2020-07-15

Applicant: Applied Materials, Inc.

Inventor： Jinrui Guo ,  Jingmei Liang ,  Praket P. Jha ,  Li Zhang

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/02 ,  C23C16/34

Abstract: Methods for forming a smooth ultra-thin flowable CVD film by using a surface treatment on a substrate surface before flowable CVD film deposition improves the uniformity and overall film smoothness. The flowable CVD film can be cured by any suitable curing process to form a smooth flowable CVD film.

公开(公告)号：US11152248B2

公开(公告)日：2021-10-19

申请号：US16882989

申请日：2020-05-26

Applicant: Applied Materials, Inc.

Inventor： Jingmei Liang ,  Yong Sun ,  Jinrui Guo ,  Praket P. Jha ,  Jung Chan Lee ,  Tza-Jing Gung ,  Mukund Srinivasan

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/67 ,  C23C16/455 ,  H01J37/32 ,  C23C16/36 ,  C23C16/40 ,  C23C16/32 ,  C23C16/30 ,  C23C16/34 ,  C23C16/505 ,  C23C16/04

Abstract: Embodiments disclosed herein relate to cluster tools for forming and filling trenches in a substrate with a flowable dielectric material. In one or more embodiments, a cluster tool for processing a substrate contains a load lock chamber, a first vacuum transfer chamber coupled to the load lock chamber, a second vacuum transfer chamber, a cooling station disposed between the first vacuum transfer chamber and the second vacuum transfer chamber, a factory interface coupled to the load lock chamber, a plurality of first processing chambers coupled to the first vacuum transfer chamber, wherein each of the first processing chambers is a deposition chamber capable of performing a flowable layer deposition, and a plurality of second processing chambers coupled to the second vacuum transfer chamber, wherein each of the second processing chambers is a plasma chamber capable of performing a plasma curing process.