公开(公告)号：US20240045653A1

公开(公告)日：2024-02-08

申请号：US17878277

申请日：2022-08-01

Applicant: Arm Limited

Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

IPC: G06F5/01

CPC classification number: G06F5/012

Abstract: An apparatus and method of converting data into an Enhanced Block Floating Point (EBFP) format with a shared exponent is provided. The EBFP format enables data within a wide range of values to be stored using a reduced number of bits compared with conventional floating-point or fixed-point formats. The data to be converted may be in any other format, such as fixed-point, floating-point, block floating-point or EBFP.

公开(公告)号：US20240038297A1

公开(公告)日：2024-02-01

申请号：US17874611

申请日：2022-07-27

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/1104

Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.

公开(公告)号：US20240037835A1

公开(公告)日：2024-02-01

申请号：US18362439

申请日：2023-07-31

Applicant: ARM Limited

Inventor： Daren CROXFORD ,  Sharjeel SAEED ,  Isidoros SIDERIS

IPC: G06T15/00 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/60

Abstract: There is provided an apparatus configured to operate as a shader core, the shader core configured to perform a complex rendering process comprising a rendering process and a machine learning process, the shader core comprising: one or more tile buffers configured to store data locally to the shader core, wherein during the rendering process, the one or more tile buffers are configured to store rendered fragment data relating to a tile; and during the machine learning process, the one or more tile buffers are configured to store an input feature map, kernel weights or an output feature map relating to the machine learning process.

公开(公告)号：US20240036932A1

公开(公告)日：2024-02-01

申请号：US18359002

申请日：2023-07-26

Applicant: Arm Limited

Inventor： Daren Croxford ,  Sharjeel Saeed ,  Isidoros Sideris

IPC: G06F9/50 ,  G06T15/00

CPC classification number: G06F9/505 ,  G06T15/005

Abstract: Disclosed herein is a graphics processor that comprises a programmable execution unit operable to execute programs to perform graphics processing operations. The graphics processor further comprises a dedicated machine learning processing circuit operable to perform processing operations for machine learning processing tasks. The machine learning processing circuit is in communication with the programmable execution unit internally to the graphics processor. In this way, the graphics processor can be configured such that machine learning processing tasks can be performed by the programmable execution unit, the machine learning processing circuit, or a combination of both, with the different units being able to message each other accordingly to control the processing.

公开(公告)号：US11886987B2

公开(公告)日：2024-01-30

申请号：US16451205

申请日：2019-06-25

Applicant: Arm Limited

Inventor： Shidhartha Das ,  Matthew Mattina ,  Glen Arnold Rosendale ,  Fernando Garcia Redondo

IPC: G06N3/065 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/065 ,  G06N3/04 ,  G06N3/08

Abstract: A multiply-accumulate method and architecture are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally modulates the equivalent conductance of individual networks among the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network. A first partial selection of weights within the neural network is mapped into the equivalent conductances of the networks in the columns to enable the computation of multiply-and-accumulate operations by mixed-signal computation. The logic updates the mappings to select a second partial selection of weights to compute additional multiply-and-accumulate operations and repeats the mapping and computation operations until all computations for the neural network are completed.

公开(公告)号：US11886972B2

公开(公告)日：2024-01-30

申请号：US17036490

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Paul Nicholas Whatmough ,  Glen Arnold Rosendale

IPC: G06N3/04 ,  G11C13/00 ,  G06F7/544 ,  H03M1/12 ,  H03M1/66 ,  G06N3/065 ,  G06N3/045 ,  G06N3/048 ,  G11C11/54 ,  G06N3/044

CPC classification number: G06N3/04 ,  G06F7/5443 ,  G06N3/045 ,  G06N3/048 ,  G06N3/065 ,  G11C11/54 ,  G11C13/0007 ,  G11C13/0069 ,  G06N3/044 ,  H03M1/12 ,  H03M1/66

Abstract: A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.

公开(公告)号：US20240029420A1

公开(公告)日：2024-01-25

申请号：US18339042

申请日：2023-06-21

Applicant: Arm Limited

Inventor： Liam James O’Neil ,  Joshua James Sowerby ,  Yanxiang Wang ,  Maxim Novikov

IPC: G06V10/82 ,  G06V10/77 ,  G06V10/40

CPC classification number: G06V10/82 ,  G06V10/77 ,  G06V10/40

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, techniques to process image signal intensity values sampled from a multi color channel imaging device. In particular, methods and/or techniques disclosed herein are directed to processing image signal intensity values by application of kernel coefficients to the image signal intensity values.

公开(公告)号：US20240028241A1

公开(公告)日：2024-01-25

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Steven Daniel MACLEAN ,  Nicholas Andrew PLANTE ,  Muhammad Umar FAROOQ ,  Michael Brian SCHINZLER ,  Nicholas Todd HUMPHRIES ,  Glen Andrew HARRIS

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/0673

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

公开(公告)号：US11874469B2

公开(公告)日：2024-01-16

申请号：US17649754

申请日：2022-02-02

Applicant: Arm Limited

Inventor： Daren Croxford ,  Roberto Lopez Mendez

IPC: G02B27/01 ,  G06F3/01

CPC classification number: G02B27/0172 ,  G06F3/013 ,  G02B2027/014 ,  G02B2027/0138 ,  G02B2027/0174 ,  G02B2027/0178

Abstract: A method of controlling an imaging system for a Head Mounted Display (HMD) device. The method comprises capturing an external scene, for example using a camera, determining an attenuation pattern, for rendering a filter area. The method also comprises determining, based on the captured external scene, a compensation pattern to for compensating at least part of the filter area, attenuating the external scene using the attenuation pattern and generating a holographic image of a virtual object, the holographic image including the compensation pattern.

公开(公告)号：US11869572B2

公开(公告)日：2024-01-09

申请号：US16516094

申请日：2019-07-18

Applicant: Arm Limited

Inventor： Prashant Dubey

IPC: G11C11/4074 ,  G11C5/05 ,  G11C5/14 ,  G11C11/56

CPC classification number: G11C11/4074 ,  G11C5/05 ,  G11C5/147 ,  G11C11/5628

Abstract: Various implementations described herein are directed to device having a memory array that operates with an applied core voltage. The device includes a power gating switch that receives a core supply voltage and provides the applied core voltage to the memory array. The device includes a biasing stage that selectively activates the power gating switch based on sensing a changing voltage level of the applied core voltage.