公开(公告)号：US10164524B1

公开(公告)日：2018-12-25

申请号：US15169505

申请日：2016-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin

IPC: H02M3/155 ,  G11C7/20 ,  G06F1/32 ,  G11C11/4074

Abstract: Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two of the PMOS transistors within the PMOS cross quad. Transmission gates are also employed to engage and disengage the charge pump based on a control switch. In various embodiments, the level translator device works with a number of memory devices operating over a wide range of power supply voltages.

公开(公告)号：US10153774B1

公开(公告)日：2018-12-11

申请号：US15418327

申请日：2017-01-27

Applicant: Cadence Design Systems, Inc.

Inventor： Scott David Huss ,  Mark Alan Summers

IPC: H03L7/06 ,  H03L7/093 ,  H03F3/45

Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.

公开(公告)号：US10133837B1

公开(公告)日：2018-11-20

申请号：US15405623

申请日：2017-01-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Ophir Turbovich ,  Yosinori Watanabe ,  Michael Young ,  Sean Dart

IPC: G06F17/50 ,  G06F7/483

Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

公开(公告)号：US10133292B1

公开(公告)日：2018-11-20

申请号：US15191678

申请日：2016-06-24

Applicant: Cadence Design Systems, Inc.

Inventor： Mark Alan Summers ,  Scott David Huss

IPC: G05F3/26

Abstract: Systems disclosed herein provide for a low-noise current mirror operable under low power supply requirements. Embodiments of the systems provide for a low input current path and a high input current path, wherein the current in the low current input path sees a higher voltage and the current in the high input current path sees a lower voltage. Embodiments of the system also provide for a cascode transistor in the high input current path.

公开(公告)号：US10114920B1

公开(公告)日：2018-10-30

申请号：US15197142

申请日：2016-06-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Umesh Gupta ,  Shashank Tripathi ,  Naresh Kumar ,  Arvind Nembili Veeravalli ,  Prashant Sethia ,  Ritika Govila

IPC: G06F17/50

Abstract: A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

公开(公告)号：US10102328B1

公开(公告)日：2018-10-16

申请号：US15060020

申请日：2016-03-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Jay Alpert ,  Mehmet Can Yildiz

IPC: G06F17/50

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.

公开(公告)号：US10055528B1

公开(公告)日：2018-08-21

申请号：US15282739

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/74

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the figure group based in part or in whole upon one or more criteria and update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

公开(公告)号：US10031994B1

公开(公告)日：2018-07-24

申请号：US15219008

申请日：2016-07-25

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Wen Hao Liu ,  Jhih-Rong Gao ,  Mehmet Yildiz ,  Charles Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.

公开(公告)号：US10031986B1

公开(公告)日：2018-07-24

申请号：US15086654

申请日：2016-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Vishnu Kumar ,  Manuj Verma

IPC: G06F17/50

Abstract: The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.

公开(公告)号：US09990456B1

公开(公告)日：2018-06-05

申请号：US14674762

申请日：2015-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Randall Scott Lawson ,  Brett Allen Neal ,  Richard Allen Woodward, Jr. ,  Edmund J. Hickey

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: The present disclosure relates to a method for routing in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, the electronic circuit design having a plurality of terminal pads associated therewith. Embodiments may further include generating a change in at least one of a size or an existence of at least one of the plurality of terminal pads. Embodiments may also include routing a portion of the electronic design based upon, at least in part, the generated change.