公开(公告)号：US11791626B2

公开(公告)日：2023-10-17

申请号：US17490371

申请日：2021-09-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Mickey Yu ,  Robert J. Gauthier, Jr.

IPC: H02H9/04 ,  H01L27/02 ,  H02H1/00 ,  H01L23/60

CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0288 ,  H01L27/0292 ,  H02H1/0007

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

公开(公告)号：US11791334B2

公开(公告)日：2023-10-17

申请号：US17075056

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L27/08 ,  H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/0646 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US20230326520A1

公开(公告)日：2023-10-12

申请号：US17658189

申请日：2022-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/412 ,  H03K3/356

CPC classification number: G11C11/419 ,  G11C11/412 ,  H03K3/356078 ,  H03K3/356026

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20230317627A1

公开(公告)日：2023-10-05

申请号：US17707273

申请日：2022-03-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Siva P. ADUSUMILLI ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC: H01L23/552 ,  H01L29/737 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L23/552 ,  H01L29/7371 ,  H01L29/0649 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with airgap structures and methods of manufacture. The structure includes: a semiconductor substrate with a trap-rich region; one or more airgap structures within the semiconductor substrate; at least one deep trench isolation structure laterally surrounding the one or more airgap structures and extending into the semiconductor substrate; and a device over the one or more airgap structures.

公开(公告)号：US20230314708A1

公开(公告)日：2023-10-05

申请号：US17658092

申请日：2022-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： YUSHENG BIAN

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/1228 ,  G02B6/12004 ,  G02B2006/12147 ,  G02B2006/12166

Abstract: A stacked edge coupler for a photonic chip is provided. The stacked edge coupler includes an insulating layer, a waveguide core, a first assisting waveguide, and a back-end-of-line stack. The first assisting waveguide is on the insulating layer. The waveguide core is over the first assisting waveguide and includes a tapered section. The back-end-of-line stack is over the waveguide core. The back-end-of-line stack includes a side edge, a dielectric layer, and a second assisting waveguide. The second assisting waveguide is on the dielectric layer and arranged adjacent to the side edge. The second assisting waveguide has an overlapping arrangement with the tapered section of the waveguide core.

公开(公告)号：US20230314706A1

公开(公告)日：2023-10-05

申请号：US17709841

申请日：2022-03-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/12 ,  G02B6/125

CPC classification number: G02B6/12016 ,  G02B6/125 ,  G02B2006/12147

Abstract: Disclosed is a structure including a first waveguide core with a first end portion and a second waveguide core with a second end portion, which overlays and is physically separated from the first end portion. The structure includes a coupler configured for interlayer waveguide coupling. Specifically, the coupler includes an additional waveguide core stacked vertically between and physically separated from the first end portion and the second end portion. Optionally, the coupler includes multiple additional waveguide cores. The shapes of the various waveguide cores are configured in order to achieve mode matching so that optical signals pass between the first end portion of the first waveguide core and the second end portion of the second waveguide core through each additional waveguide core in sequence. Also disclosed is a structure including a crossing array implemented using couplers.

公开(公告)号：US20230314274A1

公开(公告)日：2023-10-05

申请号：US17657175

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hanyi Ding ,  Aidong Yan ,  Rongtao Cao

IPC: G01M11/00 ,  G02B6/42

CPC classification number: G01M11/00 ,  G02B6/4206

Abstract: A structure for testing a photodiode in a PIC using a grating coupler in optical communication with an optical terminal in a different location of the photodiode from another optical terminal used during operation of the PIC. The photodiode includes an operational optical terminal and a test optical terminal with the test optical terminal in a different location than the operational optical terminal. An optical component is in optical communication with the operational optical terminal of the photodiode and is used during operation of the photodiode and the PIC. A grating coupler is in optical communication with the test optical terminal of the photodiode for testing purposes.

公开(公告)号：US20230305242A1

公开(公告)日：2023-09-28

申请号：US17705911

申请日：2022-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/42

CPC classification number: G02B6/4203

Abstract: Photonics structures including a slotted waveguide and methods of fabricating such photonics structures. The photonics structure includes a slotted waveguide having a first waveguide core and a second waveguide core laterally positioned adjacent to the first waveguide core. The first waveguide core is separated from the second waveguide core by a slot. The photonics structure further includes a metamaterial structure having a plurality of elements separated by a plurality of gaps and a dielectric material in the plurality of gaps. The metamaterial structure and the slot of the slotted waveguide are positioned with an overlapping arrangement.

公开(公告)号：US11769806B2

公开(公告)日：2023-09-26

申请号：US17525236

申请日：2021-11-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Jagar Singh

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/737 ,  H01L29/735

CPC classification number: H01L29/41708 ,  H01L29/401 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer having a top surface and a side surface, a second terminal having a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further includes a contact positioned to overlap with the top surface and the side surface of the first raised semiconductor layer.

公开(公告)号：US20230299132A1

公开(公告)日：2023-09-21

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  Rajendran KRISHNASAMY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L21/763 ,  H01L29/165

CPC classification number: H01L29/0642 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/7371 ,  H01L21/763 ,  H01L29/165

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.