公开(公告)号：US20130141858A1

公开(公告)日：2013-06-06

申请号：US13689070

申请日：2012-11-29

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hong Beom PYEON

IPC: G06F1/18

CPC classification number: G06F1/18 ,  G06F1/203 ,  G06F15/78 ,  G11C11/401 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A multi-chip package has a substrate with electrical contacts for connection to an external device. A CPU die is disposed on the substrate and is in communication with the substrate. The CPU die has a plurality of processor cores occupying a first area of the CPU die, and an SRAM cache occupying a second area of the CPU die. A DRAM cache is disposed on the CPU die and is in communication with the CPU die. The DRAM cache has a plurality of stacked DRAM die. The plurality of stacked DRAM dies are substantially aligned with the second area of the CPU die, and substantially do not overlap the first area of the CPU die. A multi-chip package having a DRAM cache disposed on the substrate and a CPU die disposed on the DRAM cache is also disclosed.

Abstract translation: 多芯片封装具有具有用于连接到外部设备的电触点的基板。 CPU芯片设置在基板上并且与基板连通。 CPU管芯具有占用CPU管芯的第一区域的多个处理器核和占据CPU管芯的第二区域的SRAM缓存。 DRAM缓存器设置在CPU管芯上并与CPU管芯通信。 DRAM高速缓存具有多个堆叠的DRAM裸片。 多个堆叠的DRAM裸片基本上与CPU裸片的第二区域对齐，并且基本上不与CPU裸片的第一区域重叠。 还公开了具有设置在基板上的DRAM高速缓存和设置在DRAM高速缓存上的CPU管芯的多芯片封装。

公开(公告)号：US20130137296A1

公开(公告)日：2013-05-30

申请号：US13751825

申请日：2013-01-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Yehuda BINDER

IPC: H04M7/00

CPC classification number: H04M7/0003 ,  H04L12/2803 ,  H04L12/2838 ,  H04L2012/2843 ,  H04L2012/2845 ,  H04L2012/285 ,  H04M11/062

Abstract: An outlet for coupling at least one data unit to digital data carried over wiring that simultaneously carry a packet-based serial digital data signal and a power signal over the same conductors. The outlet includes: a wiring connector for connecting to the wiring; a transceiver coupled to the wiring connector for transmitting and receiving packet-based serial digital data over the wiring; a LAN connector coupled to the transceiver for bi-directional packet-based data communication with at least one data unit; a bridge or a router coupled between the transceiver and the LAN connector for passing data bi-directionally between the at least one data unit and the wiring; and a single enclosure housing the above-mentioned components. The enclosure is mountable into a standard wall outlet receptacle or wall outlet opening, and the transceiver and the bridge or router are coupled to the wiring connector to be powered from the power signal.

Abstract translation: 用于将至少一个数据单元耦合到通过布线承载的数字数据的插座，其同时携带基于分组的串行数字数据信号和通过相同导体的功率信号。 插座包括：用于连接到接线的接线连接器; 耦合到布线连接器的收发器，用于通过布线发送和接收基于分组的串行数字数据; 耦合到收发器的LAN连接器，用于与至少一个数据单元的双向分组数据通信; 耦合在所述收发器和所述LAN连接器之间的桥或路由器，用于在所述至少一个数据单元和所述布线之间双向传递数据; 以及容纳上述部件的单个外壳。 外壳可安装到标准的墙壁插座或墙壁出口开口中，收发器和桥接器或路由器通过电源信号耦合到接线连接器供电。

公开(公告)号：US20130135917A1

公开(公告)日：2013-05-30

申请号：US13684260

申请日：2012-11-23

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Byoung Jin CHOI

IPC: G11C5/06

CPC classification number: H01L25/0657 ,  G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4097 ,  G11C29/023 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices 2, 3, connected to a logic device 1, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device 1 having capability to analyze and compensate for differing delays to the stacked devices 2,3,4,5 stacking multiple dice divided into partitions serviced by multiple buses 21,22 connected to a logic die 1, to increase throughput between the devices 2,3 and logic 1 device allowing large scale integration of memory with self-healing capability.

Abstract translation: 一种用于组织包括连接到逻辑设备1的多个存储器件2,3的计算机系统的存储器的方法和装置，特别是具有连接到逻辑管芯的多个堆叠的存储器管芯的存储器系统与逻辑器件1 具有分析和补偿堆叠设备2,3,4,5的不同延迟的能力，2,3,4,5将多个骰子分成多个分割成连接到逻辑管芯1的多个总线21,22所服务的分区，以增加器件2,3和 逻辑1器件允许大规模集成存储器与自我修复能力。

公开(公告)号：US20130102111A1

公开(公告)日：2013-04-25

申请号：US13713320

申请日：2012-12-13

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki Kim

IPC: H01L21/50

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  H01L21/50 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).

Abstract translation: 公开了一种包括非易失性存储器件的堆叠。 堆栈中的非易失性存储器件之一是主器件，而其余存储器件或器件是从器件。

公开(公告)号：US20130033941A1

公开(公告)日：2013-02-07

申请号：US13649403

申请日：2012-10-11

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  Peter Gillingham

IPC: G11C16/10

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract translation: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外，存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

公开(公告)号：US20130024717A1

公开(公告)日：2013-01-24

申请号：US13624487

申请日：2012-09-21

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC: G06F1/12

CPC classification number: G06F5/08

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

公开(公告)号：US20040130962A1

公开(公告)日：2004-07-08

申请号：US10645330

申请日：2003-08-21

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC: G11C008/00

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置，以及用于接收时钟输入信号并用于传送时钟的抽头延迟线 驱动信号与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

公开(公告)号：US20040036456A1

公开(公告)日：2004-02-26

申请号：US10463218

申请日：2003-06-17

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Robert F. Harland ,  Valerie L. Lines

IPC: G05F001/40

CPC classification number: G11C5/145 ,  G05F3/205 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  H02M3/07

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract translation: 用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。 升压电路中的晶体管完全切换，消除了Vtn通过晶体管降低升压电压。 升压电容器由Vdd充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

公开(公告)号：US20030107944A1

公开(公告)日：2003-06-12

申请号：US10348062

申请日：2003-01-17

Applicant: Mosaid Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC: G11C008/00

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

公开(公告)号：US20020075706A1

公开(公告)日：2002-06-20

申请号：US10056837

申请日：2002-01-24

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Robert F. Harland ,  Valerie L. Lines

IPC: H02M003/18

CPC classification number: G11C5/145 ,  G05F3/205 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  H02M3/07

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract translation: 用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。 升压电路中的晶体管完全切换，消除了Vtn通过晶体管降低升压电压。 升压电容器由Vdd充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。