公开(公告)号：US20210280240A1

公开(公告)日：2021-09-09

申请号：US16987101

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  VIPIN Tiwari

IPC: G11C11/54 ,  G11C16/28 ,  G11C16/04 ,  H03F3/00 ,  H03M1/16 ,  H03M1/38 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

公开(公告)号：US20210264996A1

公开(公告)日：2021-08-26

申请号：US17006550

申请日：2020-08-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Guangming Lin ,  Xiaozhou Qian ,  Xiao Yan Pi ,  Vipin Tiwari ,  Zhenlin Ding

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address for a physical word in the emulated EEPROM, and the index word keeps track of which physical word is the current word for a particular logical address. The use of the index word enables a wear leveling algorithm that allows for a programming command to a logical address to result in: (i) skipping the programming operation if the data stored in the current word does not contain a “1” that corresponds to a “0” in the data to be stored, (ii) reprogramming one or more bits of the current word in certain situations, or (iii) shifting to and programming the next physical word in certain situations.

公开(公告)号：US20210257023A1

公开(公告)日：2021-08-19

申请号：US17199243

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  ANH LY ,  THUAN VU ,  STANLEY HONG ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C7/06

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

公开(公告)号：US11087207B2

公开(公告)日：2021-08-10

申请号：US15991890

申请日：2018-05-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

公开(公告)号：US20210232893A1

公开(公告)日：2021-07-29

申请号：US17233006

申请日：2021-04-16

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： FARNOOD MERRIKH BAYAT ,  XINJIE GUO ,  DMITRI STRUKOV ,  NHAN DO ,  HIEU VAN TRAN ,  VIPIN TIWARI ,  MARK REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G06F3/06

Abstract: Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a converter for converting a target weight into a target current and a comparator for comparing the target current to an output current from the selected non-volatile memory cell during a verify operation. In another embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a digital-to-analog converter for converting a target weight comprising digital bits into a target voltage, a current-to-voltage converter for converting an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator for comparing the output voltage to the target voltage during a verify operation.

公开(公告)号：US11069411B2

公开(公告)日：2021-07-20

申请号：US16574059

申请日：2019-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/24 ,  G11C16/04

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.

公开(公告)号：US20210167762A1

公开(公告)日：2021-06-03

申请号：US16838847

申请日：2020-04-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Ryan Mei ,  XIAOZHOU QIAN ,  HIEU VAN TRAN ,  CLAIRE ZHU

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/003 ,  H03K19/185

Abstract: An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.

公开(公告)号：US20210035643A1

公开(公告)日：2021-02-04

申请号：US17075691

申请日：2020-10-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Kha Nguyen ,  Hien Pham ,  Stanley Hong ,  Stephen T. Trinh

IPC: G11C16/14 ,  H02M3/07 ,  G11C16/30

Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.

公开(公告)号：US10910061B2

公开(公告)日：2021-02-02

申请号：US15990395

申请日：2018-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G06N3/063

Abstract: Numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20210020255A1

公开(公告)日：2021-01-21

申请号：US16569611

申请日：2019-09-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/08 ,  G06F3/06 ,  G06N3/063

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.