公开(公告)号：US07667247B2

公开(公告)日：2010-02-23

申请号：US11745862

申请日：2007-05-08

Applicant: Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

Inventor： Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

IPC: H01L29/80 ,  H01L31/112

CPC classification number: H01L21/28185 ,  H01L21/2822 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成电介质层，用含碳基团处理电介质层，在经处理的电介质层上形成导电层，以及图案化和蚀刻电介质层和导电层以形成 门结构。 含碳基团包括OCH 3或CN物质。

公开(公告)号：US07646068B2

公开(公告)日：2010-01-12

申请号：US11483913

申请日：2006-07-10

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/76 ,  H01L29/00

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Abstract translation: 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128.应变沟道晶体管132形成在第二有源区域中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US20090314739A1

公开(公告)日：2009-12-24

申请号：US12345896

申请日：2008-12-30

Applicant: CHIH-KANG YANG ,  WEN-CHIN LEE

Inventor： CHIH-KANG YANG ,  WEN-CHIN LEE

IPC: B44C1/22 ,  C23F1/08

CPC classification number: H05K3/0085 ,  H05K3/068 ,  H05K2203/0195 ,  H05K2203/075 ,  H05K2203/082 ,  H05K2203/1476 ,  H05K2203/1509 ,  H05K2203/166

Abstract: An exemplary system for processing a workpiece comprises a conveyor, a first liquid spraying device, a second liquid spraying device, and a substrate positioning device. The conveyor is configured for conveying the workpiece along a conveying direction. The first and second liquid spraying devices for spraying liquid onto the workpiece transported on the conveyor face the conveyor and are arranged along the conveying direction. The substrate positioning device for reorienting the workpiece on the conveyor is installed between the first and second liquid spraying devices and faces the conveyor.

Abstract translation: 用于处理工件的示例性系统包括输送机，第一液体喷射装置，第二液体喷射装置和基板定位装置。 输送机构造成沿输送方向输送工件。 第一和第二液体喷射装置，用于将液体喷射到在输送机上传送的工件上，并且沿输送方向布置。 用于在输送机上重新定向工件的基板定位装置安装在第一和第二液体喷涂装置之间并面向输送机。

公开(公告)号：US07569896B2

公开(公告)日：2009-08-04

申请号：US11438711

申请日：2006-05-22

Applicant: Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

Abstract: A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.

Abstract translation: 提供了在通道区​​域中具有优化的应力的MOS器件及其形成方法。 MOS器件包括在衬底上的栅极，栅极侧壁上的栅极间隔物，其中在栅极间隔物下方存在非硅化物区域，在衬底中包含凹陷的源极/漏极区域和源极上的硅化物区域 /漏区。 在硅化物区域的较高部分和硅化物区域的下部之间形成台阶高度。 凹槽与非硅化物区域的相应边缘间隔一定距离。 台阶高度和间距优选具有小于或等于约3的比率。非硅化物区域的宽度和台阶高度优选具有小于或等于约3的比率。MOS器件优选为 NMOS器件。

公开(公告)号：US20090107706A1

公开(公告)日：2009-04-30

申请号：US12135842

申请日：2008-06-09

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: H05K1/00

CPC classification number: H05K3/4641 ,  H05K3/386 ,  H05K2201/0382 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A multilayer printed circuit board includes a first printed circuit board, a second printed circuit board, an adhesive film, and a function layer. The adhesive film is sandwiched between the first printed circuit board and the second printed circuit board. The function layer is disposed between the first printed circuit board and the second printed circuit board for blocking water from passing therethrough and for screening electromagnetic interference between the first printed circuit board and the second printed circuit board.

Abstract translation: 多层印刷电路板包括第一印刷电路板，第二印刷电路板，粘合膜和功能层。 粘合膜夹在第一印刷电路板和第二印刷电路板之间。 功能层设置在第一印刷电路板和第二印刷电路板之间，用于阻止水从其中通过，并用于屏蔽第一印刷电路板和第二印刷电路板之间的电磁干扰。

公开(公告)号：US20090078578A1

公开(公告)日：2009-03-26

申请号：US12195844

申请日：2008-08-21

Applicant: Cheng-Hsien Lin ,  Yao-Wen Bai ,  Rui Zhang ,  Wen-Chin Lee

Inventor： Cheng-Hsien Lin ,  Yao-Wen Bai ,  Rui Zhang ,  Wen-Chin Lee

IPC: H05K3/00 ,  B82B3/00

CPC classification number: H05K3/424 ,  B82Y10/00 ,  C23C18/1204 ,  C23C18/127 ,  C23C18/1287 ,  H05K3/427 ,  H05K2201/026 ,  H05K2201/0323

Abstract: A pre-plating solution for making a printed circuit board includes carbon nanotubes of 0.01-3 wt %, a surfactant of 0.01-4 wt %, an alkaline substance of 0.01-l wt % and a solvent. A method for preparing a pre-plating solution comprising the steps of: providing a plurality of carbon nanotubes; purifying the carbon nanotubes; treating the purified carbon nanotubes with an acid; mixing the treated carbon nanotubes, an alkaline substance and a solvent to form suspension; and adding surfactant into suspension.

Abstract translation: 用于制造印刷电路板的预镀溶液包括0.01-3重量％的碳纳米管，0.01-4重量％的表面活性剂，0.01-1重量％的碱性物质和溶剂。 一种制备预镀液的方法，包括以下步骤：提供多个碳纳米管; 纯化碳纳米管; 用酸处理纯化的碳纳米管; 混合处理的碳纳米管，碱性物质和溶剂以形成悬浮液; 并将表面活性剂加入悬浮液中。

公开(公告)号：US20090050602A1

公开(公告)日：2009-02-26

申请号：US12135843

申请日：2008-06-09

Applicant: CHENG-HSIEN LIN ,  WEN-CHIN LEE ,  KAI-LI JIANG

Inventor： CHENG-HSIEN LIN ,  WEN-CHIN LEE ,  KAI-LI JIANG

IPC: H01B13/00

CPC classification number: H05K3/0038 ,  B82Y10/00 ,  H05K2201/0112 ,  H05K2201/026 ,  H05K2201/0323

Abstract: A method for forming holes in making a printed circuit board includes the step of: providing a copper clad laminate including an insulation layer and a copper layer laminated on the insulation layer; forming a carbon nano-material on the copper layer of the copper clad laminate; and applying a laser beam onto a portion of the carbon nano-material to define a hole in the copper clad laminate beneath the portion of the carbon nano-material.

Abstract translation: 一种在制造印刷电路板中形成孔的方法包括以下步骤：提供层压在绝缘层上的包括绝缘层和铜层的覆铜层压板; 在覆铜层压板的铜层上形成碳纳米材料; 以及将激光束施加到所述碳纳米材料的一部分上以在所述碳纳米材料部分之下的所述覆铜层压板中限定出一个孔。

公开(公告)号：US20090045411A1

公开(公告)日：2009-02-19

申请号：US11839352

申请日：2007-08-15

Applicant: Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/24 ,  H01L29/778

CPC classification number: H01L29/7833 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

Abstract translation: 提供半导体结构。 半导体结构包括半导体衬底; 绝缘区域，其从所述半导体衬底的大致顶表面延伸到所述半导体衬底中; 邻近所述绝缘区域的嵌入式电介质间隔件，其中所述嵌入式电介质间隔件的底部邻接所述半导体衬底; 以及邻接在顶部边缘并且在嵌入的电介质间隔物的侧壁上延伸的半导体材料。

公开(公告)号：US07459756B2

公开(公告)日：2008-12-02

申请号：US11467980

申请日：2006-08-29

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L29/76

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US07453133B2

公开(公告)日：2008-11-18

申请号：US10880992

申请日：2004-06-30

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L27/095

CPC classification number: H01L23/3192 ,  H01L23/485 ,  H01L29/161 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.

Abstract translation: 本发明的优选实施方案包括介电/金属/第二能带隙（E />）半导体/第一电极 g 衬底结构。 为了降低接触电阻，将具有较低能量带隙（2Ω）的半导体与金属接触。 第二个和第二个半导体的能带隙比第一个第二半导体的能量带隙低， 半导体，优选低于1.1eV。 此外，可以在金属上沉积介电层。 电介质层具有内置应力以补偿金属，第二和第二半导体中的应力， g 衬底。 还公开了制造该结构的过程。