公开(公告)号：US11934824B2

公开(公告)日：2024-03-19

申请号：US16841222

申请日：2020-04-06

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G06F7/544

CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30032 ,  G06F9/30043

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US20240088084A1

公开(公告)日：2024-03-14

申请号：US17943104

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Brent Keeth

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/1433 ,  H01L2924/1436

Abstract: An interface shim layer for a tightly-coupled random access memory device is disclosed. The interface shim layer redirects and coalesces integrated channels and connections between a stacked plurality of memory die and an application specific integrated circuit and directly connects to the memory die and to the application specific integrated circuit. A passive version of the interface shim layer incorporates a plurality of routing layers to facilitate routing of signals to and from the stacked plurality of memory die and the application specific integrated circuit. An active version of the interface shim layer incorporates separate physical interfaces for both the stacked plurality of memory die and the application specific integrated circuit to facilitate routing. The active version of the interface shim layer may further incorporate memory controller functions, built-in self-test circuits, among other capabilities that are migratable into the active interface shim layer.

公开(公告)号：US20230393992A1

公开(公告)日：2023-12-07

申请号：US17945702

申请日：2022-09-15

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Shivam Swami

IPC: G06F12/122 ,  G06F12/0884 ,  G06F12/0864

CPC classification number: G06F12/122 ,  G06F12/0884 ,  G06F12/0864

Abstract: Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.

公开(公告)号：US11817087B2

公开(公告)日：2023-11-14

申请号：US17006157

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel

IPC: G10L15/16 ,  G10L15/30 ,  G10L15/22 ,  G06F16/635 ,  G06N3/08

CPC classification number: G10L15/16 ,  G06F16/635 ,  G06N3/08 ,  G10L15/22 ,  G10L15/30 ,  G10L2015/221 ,  G10L2015/223

Abstract: Systems and methods for distributing cloud-based language processing services to partially execute in a local device to reduce latency perceived by the user. For example, a local device may receive a request via audio input, that requires a cloud-based service to process the request and generate a response. A partial response may be generated locally and played back while a more complete response is generated remotely.

公开(公告)号：US11789797B2

公开(公告)日：2023-10-17

申请号：US17886253

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G11C15/04 ,  G06F11/07 ,  G06F11/10 ,  G11C5/06 ,  G11C11/409

CPC classification number: G06F11/076 ,  G06F11/102 ,  G11C5/063 ,  G11C11/409 ,  G11C15/04

Abstract: Methods, systems, and devices for error control for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US20230267043A1

公开(公告)日：2023-08-24

申请号：US17652231

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10

CPC classification number: G06F11/108

Abstract: Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.

公开(公告)号：US20230214148A1

公开(公告)日：2023-07-06

申请号：US17652229

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US11693657B2

公开(公告)日：2023-07-04

申请号：US16717890

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/38 ,  G11C7/06 ,  G06F9/30 ,  G11C7/10 ,  G11C8/10

CPC classification number: G06F9/3001 ,  G06F9/3893 ,  G11C7/06 ,  G11C7/1096 ,  G11C8/10

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US11657002B2

公开(公告)日：2023-05-23

申请号：US17375455

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/1027 ,  H04W84/04

CPC classification number: G06F12/1027 ,  G06F2212/657 ,  G06F2212/68 ,  H04W84/042

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

公开(公告)号：US11650742B2

公开(公告)日：2023-05-16

申请号：US16573490

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Hongyu Wang ,  Justin M. Eno ,  Shivam Swami ,  Samuel E. Bradshaw

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0631 ,  G06F3/0607 ,  G06F3/0673 ,  G06F12/1027

Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.