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公开(公告)号：US11955194B2
公开(公告)日：2024-04-09
申请号：US18133103
申请日：2023-04-11
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Bruce A. Liikanen , Steven Michael Kientz
CPC classification number: G11C29/42 , G11C16/16 , G11C16/26 , G11C29/12015 , G11C29/44 , G11C2207/2254
Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.
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公开(公告)号：US11941277B2
公开(公告)日：2024-03-26
申请号：US18118082
申请日：2023-03-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shane Nowell , Michael Sheperek , Larry J. Koudele , Vamsi Pavan Rayaprolu
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0629 , G06F3/0653 , G06F3/0659 , G06F3/0679
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.
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公开(公告)号：US11915776B2
公开(公告)日：2024-02-27
申请号：US17943123
申请日：2022-09-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Sheperek , Kishore Kumar Muchherla , Shane Nowell , Mustafa N Kaynak , Larry J Koudele
CPC classification number: G11C29/56008 , G11C16/26
Abstract: A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.
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公开(公告)号：US11908536B2
公开(公告)日：2024-02-20
申请号：US17982346
申请日：2022-11-07
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Bruce A. Liikanen
CPC classification number: G11C29/50004 , G11C7/1051 , G11C16/10 , G11C16/34 , H04L1/203 , G11C2207/2254 , G11C2216/16
Abstract: Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device then adjusts a read level threshold of the memory cell to be centered between a first programming distribution and a second programming distribution before the second programming pass of the programming operation is performed on the memory cell.
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公开(公告)号：US20240021258A1
公开(公告)日：2024-01-18
申请号：US18373741
申请日：2023-09-27
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Michael Sheperek , Chris Smitchger
CPC classification number: G11C29/021 , G11C29/12005 , G11C29/50004 , G11C29/44 , G11C2207/2254
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric value satisfies a first threshold criterion, obtaining, from a neural network, a value of a voltage distribution metric associated with the page; and upon determining that the voltage distribution metric value satisfies a second threshold criterion, performing a media management operation with respect to a block associated with the page, wherein the media management operation comprises writing data stored at the block to a new block.
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Patent Agency Ranking
公开(公告)号：US11842772B2
公开(公告)日：2023-12-12
申请号：US17857942
申请日：2022-07-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Sheperek , Bruce A. Liikanen , Steve Kientz
CPC classification number: G11C16/10 , G06F12/0246 , G06F12/0882 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3404 , G06F2212/7207 , G11C2207/2254
Abstract: A first bin boundary for a first voltage bin associated with a die of a memory device is identified. The first bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family is determined. The first bin boundary is updated based on the first bin boundary offset.
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公开(公告)号：US11817152B2
公开(公告)日：2023-11-14
申请号：US17892721
申请日：2022-08-22
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Michael Sheperek , Larry J. Koudele
CPC classification number: G11C16/10 , G06F3/0625 , G06F3/0638 , G06F3/0679 , G11C16/26 , G11C11/56 , G11C16/0483
Abstract: A processing device determines a target bit error rate corresponding to a point of a first programming voltage distribution level corresponding to memory cells of a memory sub-system and a second programming voltage distribution corresponding to the memory cells of the memory sub-system. An offset voltage level corresponding to the point at the target bit error rate is selected. A first portion of a first group of the memory cells in the first programming voltage distribution level is programmed at a threshold voltage level to set a first embedded data value. A second portion of a second group of the memory cells in the second programming voltage distribution level is programmed at the threshold voltage level offset by the offset voltage level to set a second embedded data value.
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公开(公告)号：US11810631B2
公开(公告)日：2023-11-07
申请号：US17123993
申请日：2020-12-16
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Michael Sheperek , Christopher M. Smitchger
CPC classification number: G11C29/021 , G11C29/12005 , G11C29/44 , G11C29/50004 , G11C2207/2254
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page.
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公开(公告)号：US11735254B2
公开(公告)日：2023-08-22
申请号：US17217772
申请日：2021-03-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shane Nowell , Steven Michael Kientz , Michael Sheperek , Mustafa N Kaynak , Kishore Kumar Muchherla , Larry J Koudele , Bruce A Liikanen
CPC classification number: G11C11/5642 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/30
Abstract: A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.
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公开(公告)号：US11721409B2
公开(公告)日：2023-08-08
申请号：US17877810
申请日：2022-07-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vamsi Pavan Rayaprolu , Shane Nowell , Michael Sheperek , Steven Michael Kientz
CPC classification number: G11C29/44 , G11C16/349 , G11C29/10 , G11C29/12015 , G11C29/42 , G11C2207/2254
Abstract: A system can include a memory device and a processing device to perform operations that include determining a calibration scan frequency based on an amount of elapsed time since a previous write operation performed on the memory device, determining, based on the calibration scan frequency, whether one or more scan criteria are satisfied, responsive to determining that the one or more scan criteria are satisfied, identifying one or more block families, and calibrating one or more bin pointers of each of the identified block families, wherein the calibrating comprises: for each of the identified block families, updating each of the one or more bin pointers of the identified block family based on a data state metric of at least one block of the identified block family.
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