公开(公告)号：US20240347913A1

公开(公告)日：2024-10-17

申请号：US18300067

申请日：2023-04-13

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01Q9/04 ,  H01Q1/22

CPC classification number: H01Q9/0407 ,  H01Q1/2283

Abstract: An antenna module as a radio-frequency (RF) integrated circuit (IC) semiconductor die (“die”) with an integrated antenna substrate. The die with the integrated antenna substrate can be provided as part of a single IC chip that is fabricated as part of a wafer-level fabrication process as an example. The antenna elements are formed in one more antenna layers as part of an antenna substrate. The antenna layers may be formed as re-distribution layers (RDLs) for example to support smaller line-spacing (LS) and/or smaller pitched metal interconnects for forming and interconnecting to smaller wavelength antenna elements for supporting higher frequency communications. The antenna substrate is formed on a semiconductor wafer of an IC as part of the die. In this manner, the antenna layers can be formed as part of a wafer-level fabrication process used to form the die to form the antenna layers.

公开(公告)号：US12046530B2

公开(公告)日：2024-07-23

申请号：US17558508

申请日：2021-12-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H01L21/48 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L21/4871 ,  H01L25/0655 ,  H01L25/50

Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.

公开(公告)号：US11769732B2

公开(公告)日：2023-09-26

申请号：US17024214

申请日：2020-09-17

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Aniket Patil

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

Abstract: An integrated circuit (IC) with reconstituted die interposer for improved connectivity has at least one device or component mounted on an exterior upper surface that couples to a die in an interposer layer within the package. The interposer layer may have interconnect structures, where a first interconnect structure has vias of a first pitch and a second interconnect structure has vias of a second pitch greater than the first pitch. In this manner, the interposer layer acts as a device that can allow conductive coupling for other devices with those pitches to support interconnections between those devices and other devices within the interposer layer.

公开(公告)号：US20230268637A1

公开(公告)日：2023-08-24

申请号：US17652328

申请日：2022-02-24

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01Q1/22 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01Q1/2283 ,  H01L23/3672 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/20 ,  H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L24/19 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2225/1094

Abstract: Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies (“dies”) so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.

公开(公告)号：US20220344250A1

公开(公告)日：2022-10-27

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US11310911B2

公开(公告)日：2022-04-19

申请号：US16929004

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jonghae Kim ,  Periannan Chidambaram

IPC: H05K1/11 ,  G06F1/18 ,  H05K3/10 ,  H05K3/40 ,  H05K1/02

Abstract: An integrated circuit (IC) package is described. The IC package includes a metallization structure. The IC package also includes a first die in a package substrate layer. The package substrate includes a first surface and a second surface, opposite the first surface. The second surface of the package substrate layer is on the metallization structure. The IC package further includes a second die on the first surface of the package substrate layer and on the first die. The IC package also includes through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure. The IC package further includes package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.

公开(公告)号：US20210271275A1

公开(公告)日：2021-09-02

申请号：US16804474

申请日：2020-02-28

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Ravindra Vaman Shenoy ,  Milind Shah ,  Evgeni Gousev ,  Periannan Chidambaram

IPC: G05F1/56 ,  H02M7/155 ,  H01F27/28 ,  H01F41/04

Abstract: Reducing the space occupied by a voltage regulation integrated circuit (IC) that includes an inductor is achieved by implementing the inductor as a 3D inductor having windings formed of conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate, and positioning other components within a core space of the 3D inductor in the circuit layer. The space occupied by the inductor is shared with the other circuit components and with the structural layers of the voltage regulation IC. A voltage regulation IC may be a switched-mode power supply (SMPS) that includes an inductor with a capacitor and/or a switching circuit. The inductor is implemented as upper horizontal traces in an upper substrate, lower horizontal traces in a lower substrate, and vertical interconnects in a circuit layer between the upper substrate and the lower substrate, and the conductive elements form the 3D inductor as a rectangular coil.

公开(公告)号：US11024454B2

公开(公告)日：2021-06-01

申请号：US15191203

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  Chengjie Zuo ,  David Francis Berdy

IPC: H01F5/00 ,  H01F27/28 ,  H01F41/04 ,  H03H7/01 ,  H03F15/00 ,  H01F17/00 ,  H01F27/24

Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.

公开(公告)号：US10582609B2

公开(公告)日：2020-03-03

申请号：US15798071

申请日：2017-10-30

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Jonghae Kim ,  Xiaoju Yu ,  Mario Francisco Velez ,  Wei-Chuan Chen ,  Niranjan Sunil Mudakatte ,  Matthew Michael Nowak ,  Christian Hoffmann ,  Rodrigo Pacher Fernandes ,  Manuel Hofer ,  Peter Bainschab ,  Edgar Schmidhammer ,  Stefan Leopold Hatzl

IPC: H05K1/02 ,  H05K3/32 ,  H03H9/02 ,  H03H9/10 ,  H03H3/02 ,  H03H9/05 ,  H03H3/08

Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.

公开(公告)号：US10325855B2

公开(公告)日：2019-06-18

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.