公开(公告)号：US20250089295A1

公开(公告)日：2025-03-13

申请号：US18957156

申请日：2024-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Yen-Ru Lee ,  Chien-Chang Su ,  Chih-Yun Chin ,  Chien-Wei Lee ,  Pang-Yen Tsai ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

公开(公告)号：US12249592B2

公开(公告)日：2025-03-11

申请号：US17648236

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Cheng-I Chu ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/00 ,  H01L21/66 ,  H01L23/00

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

公开(公告)号：US12237211B2

公开(公告)日：2025-02-25

申请号：US17377667

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Chang ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

公开(公告)号：US12211901B2

公开(公告)日：2025-01-28

申请号：US17869321

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bau-Ming Wang ,  Che-Fu Chiu ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device may include a semiconductor fin, a source/drain region extending from the semiconductor fin, and a gate electrode over the semiconductor fin. The semiconductor fin may include a first well and a channel region over the first well. The first well may have a first dopant at a first dopant concentration and the channel region may have the first dopant at a second dopant concentration smaller than the first dopant concentration. The first dopant concentration may be in range from 1017 atoms/cm3 to 1019 atoms/cm3.

公开(公告)号：US12170228B2

公开(公告)日：2024-12-17

申请号：US18366864

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yao Chen ,  Pin-Chu Liang ,  Hsueh-Chang Sung ,  Pei-Ren Jeng ,  Yee-Chia Yeo

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

公开(公告)号：US20240395810A1

公开(公告)日：2024-11-28

申请号：US18790122

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment includes a device including a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first carbon-containing buffer layer on the first fin. The device also includes and a first epitaxial structure on the first carbon-containing buffer layer.

公开(公告)号：US20240387742A1

公开(公告)日：2024-11-21

申请号：US18786529

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

公开(公告)号：US20240321751A1

公开(公告)日：2024-09-26

申请号：US18654111

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US12087845B2

公开(公告)日：2024-09-10

申请号：US17236535

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ao Chang ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/67 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/67017 ,  H01L21/823431

Abstract: A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.

公开(公告)号：US20240266398A1

公开(公告)日：2024-08-08

申请号：US18636490

申请日：2024-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I Kuo ,  Wei Hao Lu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.