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419 条记录 (耗时 0.06 秒)

    Nonvolatile semiconductor memory device
    131.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US06342715B1

    公开(公告)日：2002-01-29

    申请号：US09097258

    申请日：1998-06-15

    申请人： Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshiharu Watanabe ,  Kazuhito Narita

    发明人： Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshiharu Watanabe ,  Kazuhito Narita

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.

    Semiconductor device and manufacturing method thereof
    134.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    具有嵌入元件隔离膜的半导体器件

    公开(公告)号：US06222225B1

    公开(公告)日：2001-04-24

    申请号：US09405838

    申请日：1999-09-27

    申请人： Takuya Nakamura ,  Naoki Koido ,  Hirohisa Iizuka ,  Kazuhito Narita ,  Seiichi Aritome ,  Fumitaka Arai

    发明人： Takuya Nakamura ,  Naoki Koido ,  Hirohisa Iizuka ,  Kazuhito Narita ,  Seiichi Aritome ,  Fumitaka Arai

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.

    摘要翻译： 半导体器件具有半导体衬底，在从所述半导体衬底的表面突出的状态下嵌入形成在所述半导体衬底中的沟槽中的元件隔离绝缘膜和设置在由所述元件隔离包围的区域中的栅电极的晶体管 绝缘膜，并且包含在嵌入所述元件隔离绝缘膜之前通过栅极绝缘膜沉积的栅电极，并且所述元件隔离绝缘膜的上边缘角被选择性地凹入。 在这样构成的半导体器件中，元件隔离绝缘膜的上边缘角在栅电极的图案化处理之前是凹进的，从而防止了在栅电极的图案化处理中栅电极的一部分未被蚀刻的情况 。

    Nonvolatile semiconductor memory device
    135.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5889304A

    公开(公告)日：1999-03-30

    申请号：US884555

    申请日：1997-06-27

    申请人： Hiroshi Watanabe ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Seiichi Aritome

    发明人： Hiroshi Watanabe ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Seiichi Aritome

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

    摘要： Disclosed is the memory cell of an EEPROM having a p-type silicon substrate and a floating gate formed on this silicon substrate via a tunnel oxide film. The element region set in the silicon substrate projects from the surface of a trench-type element isolation region. The projecting element region has a curved portion for increasing the density of tunnel electric current, and is rounded to concentrate the tunnel electric current as far as no breakdown occurs in the tunnel oxide film.

    摘要翻译： 公开了具有通过隧道氧化物膜形成在该硅衬底上的p型硅衬底和浮栅的EEPROM的存储单元。 设置在硅衬底中的元件区域从沟槽型元件隔离区域的表面突出。 投影元件区域具有用于增加隧道电流密度的弯曲部分，并且在隧道氧化物膜中不发生击穿的情况下，将隧道电流进行四舍五入以集中。

    Memory cell operation
    136.
    发明授权
    Memory cell operation 有权
    存储单元操作

    公开(公告)号：US08787090B2

    公开(公告)日：2014-07-22

    申请号：US13372669

    申请日：2012-02-14

    申请人： Akira Goda ,  Seiichi Aritome

    发明人： Akira Goda ,  Seiichi Aritome

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3468

    摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.

    摘要翻译： 本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。 一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数 脉冲。

    Programming method of non-volatile memory device
    138.
    发明授权
    Programming method of non-volatile memory device 有权
    非易失性存储器件的编程方法

    公开(公告)号：US08493792B2

    公开(公告)日：2013-07-23

    申请号：US13309760

    申请日：2011-12-02

    申请人： Seiichi Aritome ,  Soo Jin Wi

    发明人： Seiichi Aritome ,  Soo Jin Wi

    IPC分类号： G11C16/06 ,  G11C11/56

    CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/349

    摘要： A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number of passed memory cells corresponding to a number of pass bits, if, a result of the program verify operation, the program operation failed to program all of the memory cells of the selected page to the target threshold voltage or higher, and making a determination that determines whether the number of pass bits is greater than the first number of pass permission bits, and raising a voltage of a bit line coupled to a failed memory cell, if, as a result of the determination, the number of pass bits is greater than the first number of pass permission bits.

    摘要翻译： 一种编程方法，包括设置位线的电压，执行编程操作，通过提供编程验证电压并确定所选择的页面的所有存储单元是否已经被编程为目标阈值电压或更高，执行编程验证操作， 对与多个通过位相对应的经过的存储单元的数量进行计数，如果程序验证操作的结果，程序操作不能将所选页的所有存储单元编程为目标阈值电压或更高，并且使 确定通过位的数量是否大于第一数量的通过许可位，并且提高耦合到故障存储器单元的位线的电压，如果作为确定的结果，通过位的数量 大于第一个通过许可位数。

    Devices and memory arrays including bit lines and bit line contacts
    139.
    发明授权
    Devices and memory arrays including bit lines and bit line contacts 有权
    器件和存储器阵列，包括位线和位线触点

    公开(公告)号：US08446011B2

    公开(公告)日：2013-05-21

    申请号：US13243510

    申请日：2011-09-23

    申请人： Seiichi Aritome

    发明人： Seiichi Aritome

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/11519 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines.

    摘要翻译： 装置的每个第一位线具有上表面和下表面，其中上表面比下表面更向外位于半导体表面之上。 器件的第二位线具有上表面和下表面，其上表面比下表面更向外位于半导体表面之上。 第二位线的上表面比第一位线的上表面更向外位于半导体表面之上。 第一位线各自与第二位线相邻，并且第二位线被配置为选择性地耦合到除了​​第一位线被配置为选择性耦合的存储器单元之外的存储器单元。 第二位线不与第一位线重叠。