Abstract:
A bootstrapped CMOS driver circuit capable of driving large capacitance loads with small internal delays. Higher driving capability is achieved by using only n-channel transistors at the output and overdriving the transistors during the transitions. A total internal delay of less than one nanosecond for a driver may be provided with 100 ohms compatible output impedance.
Abstract:
A method of selectively fabricating metallization on a dielectric substrate is disclosed. A seed layer is sputtered on a polymer dielectric, a patterned photoresist mask is disposed over the seed layer, exposed portions of the seed layer are etched, the photoresist is stripped, and copper is deposited without a mask by electroless plating on the unetched seed layer to form well-adhering high density copper lines without exposing the photoresist to the electroless bath.
Abstract:
A method is provided for fabricating a display cathode which includes forming a conductive line adjacent a face of a substrate. A region of amorphic diamond is formed adjacent a selected portion of the conductive line.
Abstract:
Multicell system and method for making a multicell system. Systems include relatively thin (less than about 50 mil) electrochemical cells layered upon one another to minimize volume and weight. Cells systems are formed with cells that are layered such that first charge sides of each cell are coupled to first charge sides of other cells, and such that second charge sides of each cell are coupled to second charge sides of other cells. Cells and/or cell systems is connected to other cells and/or cell systems to form battery systems by layering cells such that a first charge side of a cell are coupled to second charge side of another cell. In this manner the number of electrically insulating separators is reduced, thereby also reducing weight and volume of resulting systems.
Abstract:
A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements. Carrier tape bonds the integrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.
Abstract:
A method of making sub-micron low work function field emission tips without using photolithography. The method includes physical vapor deposition of randomly located discrete nuclei to form a discontinuous etch mask. In one embodiment an etch is applied to low work function material covered by randomly located nuclei to form emission tips in the low work function material. In another embodiment an etch is applied to base material covered by randomly located nuclei to form tips in the base material which are then coated with low work function material to form emission tips. Diamond is the preferred low work function material.
Abstract:
Direct fabrication of three-dimensional metal parts by irradiating a thin layer of a mixture of metal powder and temperature equalization and unification vehicle to melt the metal powder and form a solid metal film. The vehicle also protects the molten metal from oxidation. The metal powder can contain an elemental metal or several metals, the vehicle can be an organic resin or an amalgam, and the irradiation can be selectively applied by a YAG laser.
Abstract:
An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.
Abstract:
An improved cathode for a sputtering system includes a metal cylinder and strips of material bonded to the inside of the metal cylinder and/or material sprayed onto the inside of the metal cylinder. The strips may have various specified compositions and/or configurations and/or other characteristics which enhance the ability of the sputtering system to deposit films of high temperature superconductor material on substrates.
Abstract:
Three-dimensional metal parts are fabricated by irradiating a thin layer of a mixture of metal powder and temperature equalization and unification vehicle to melt the metal powder and form a solid metal film. The vehicle also protects the molten metal from oxidation. The metal powder can contain an elemental metal or several metals, the vehicle can be an organic resin or an amalgam, and the irradiation can be selectively applied by a YAG laser.