公开(公告)号：US09985665B1

公开(公告)日：2018-05-29

申请号：US15282567

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Philippe Salib

IPC: H03K19/0175 ,  H03K3/012 ,  H04B1/04 ,  H04L7/027

CPC classification number: H04B1/04 ,  H03K19/0175 ,  H03K19/017581 ,  H04L7/0276

Abstract: A method, control apparatus, and system for re-establishing a common mode in a transmitter involve switching a driver circuit of the transmitter to a quick charge or quick discharge mode based on an output value of the transmitter. When the output later exceeds a programmable common mode voltage, the driver circuit is switched to a classical margining mode to bring the output back towards the targeted common mode voltage. The modes are switched by adjusting the number of activated pull-up and pull-down segments. More pull-up segments and less pull-down segments are activated in the quick charge mode than the classical margining mode. More pull-down segments and less pull-up segments are activated in the quick discharge mode than the classical margining mode.

公开(公告)号：US09940260B1

公开(公告)日：2018-04-10

申请号：US15400235

申请日：2017-01-06

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Anne Hughes ,  Bikram Banerjee

IPC: G06F12/10 ,  G06F3/06 ,  G11C5/02

CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0673 ,  G06F2212/65 ,  G11C5/02

Abstract: A memory controller system optimally controls access to a memory device having a plurality of integrated circuit (IC) chips disposed in a non-uniform stack configuration within a three-dimensional stacked (3DS) structure. A memory profiling portion executes to determine the non-uniform stack configuration. A virtual rank mapping portion configured to assign virtual ranks to chip locations actually defined by the non-uniform stack configuration. An address conversion portion executes to convert an unoptimized address definable with reference to a uniform stack configuration to an optimized address defined with reference to the non-uniform stack configuration. The addressing overhead during monitoring of data access operations to the memory device is optimized.

公开(公告)号：US09922209B1

公开(公告)日：2018-03-20

申请号：US15269919

申请日：2016-09-19

Applicant: Cadence Design Systems, Inc.

Inventor： Victor Markus Purri ,  Caio Araújo Teixeira Campos ,  Magnus Björk ,  Lawrence Loh ,  Claudionor Jose Nunes Coelho

IPC: G06F17/50 ,  G06F11/22 ,  G06F21/71

CPC classification number: G06F21/71 ,  G06F17/5022 ,  G06F17/5045 ,  G06F21/76

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

公开(公告)号：US09916403B1

公开(公告)日：2018-03-13

申请号：US15199939

申请日：2016-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Nityanand Rai ,  Hui Zheng ,  Xin Gu

IPC: G06F17/50

CPC classification number: G06F17/5009

Abstract: An improved approach is provided for determining differential voltages for driver and receiver pairs as a result of electrostatic discharge (ESD) events including identifying circuits of interest, re-characterizing the circuits of interest into a system for evaluating differential voltages, determining the differential voltages for ESD pin locations, and outputting results after iterating through all the ESD pin locations. In some embodiments, re-characterizing may include performing a resistance only extraction of a net, attaching a resistance to any node in the circuit and to ground, formulating a conductance matrix and distributing the total current I as source points. In some embodiments, determining differential voltages for ESD pin locations may include, stamping a first ESD pin location with a total current, solving for the system using previously computed values, mapping the driver and receiver pairs to the nodes in the system, computing the differential voltage, and recording the lowest differential voltage.

公开(公告)号：US09904756B1

公开(公告)日：2018-02-27

申请号：US14675516

申请日：2015-03-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Roland Ruehl ,  Alexandre Arkhipov ,  Giles V. Powell ,  Karun Sharma

IPC: G06F17/50 ,  H01L27/00 ,  G03F1/00 ,  G03F7/00 ,  G03F1/70 ,  G03F7/20 ,  H01L27/02

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G03F7/70425 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  H01L27/0207

Abstract: Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.

公开(公告)号：US09886987B1

公开(公告)日：2018-02-06

申请号：US14585621

申请日：2014-12-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sandeep Brahmadathan ,  Jeffrey Scott Earl

IPC: G11C7/10 ,  G06F1/08

CPC classification number: G11C7/1072 ,  G06F1/08 ,  G11C7/1009 ,  G11C29/023 ,  G11C29/028 ,  G11C29/56012 ,  G11C2207/2254

Abstract: A system and method providing timing alignment of a data mask (DM) signal with respect to a data strobe (DQS) signal for memory devices not designed for adjusting such alignment is provided. Alignment between data signals (DQ) and a DQS signal is first achieved during a first write training procedure where a data delay value is optimized for one of the DQS or DQ signals. Subsequently, using the optimum delay value from the first write training procedure, a second write training procedure is initiated. In the second write training procedure, timing alignment between the DM signal and the DQ signals is achieved by determining an optimal delay value of the DM signal relative to the DQS signal.

公开(公告)号：US09881123B1

公开(公告)日：2018-01-30

申请号：US15198635

申请日：2016-06-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Ratnakar Goyal ,  Manuj Verma ,  Igor Keller ,  Arvind Nembili Veeravalli

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/82

Abstract: A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.

公开(公告)号：US09881120B1

公开(公告)日：2018-01-30

申请号：US14871735

申请日：2015-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Steven Durrill ,  Taranjit Singh Kukal

IPC: G06F17/50 ,  G06F7/76 ,  G06F1/26 ,  G06F15/78

CPC classification number: G06F17/5081 ,  G06F1/266 ,  G06F7/76 ,  G06F15/7867 ,  G06F17/5018 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5063 ,  G06F2217/80 ,  H01L23/50 ,  H05K1/0203 ,  H05K3/0005

Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

公开(公告)号：US09875329B1

公开(公告)日：2018-01-23

申请号：US14983288

申请日：2015-12-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sunil Todi ,  Amit Khurana ,  Chandra Manglani

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A host system for transferring data to a target system is provided. The host system may include a layout database for storing mask layout data representing an integrated circuit (IC) in terms of planar geometric shapes. The hosts system may further include a processor configured to import the mask layout data from the layout database to a memory-mapped disk in the host system. The processor is further configured to translate the mask layout data into one or more cell views according to a table hierarchy in the memory-mapped disk. The processor is further configured to transmit the one or more cell views from the memory-mapped disk to a magnetic disk of the target system.

公开(公告)号：US09864827B1

公开(公告)日：2018-01-09

申请号：US14973064

申请日：2015-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Jilin Tan ,  Jian Chen ,  Jian Liu ,  An-Yu Kuo ,  Tiejun Yu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: The present disclosure relates to a system and method for modeling an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design. Embodiments may also include partitioning, at a graphical user interface configured to display at least a portion of the electronic circuit design, at least one portion of the electronic circuit design into one or more sub-zones and generating, at the graphical user interface, one or more ports at each interface between one or more sub-zones. Embodiments may further include receiving a selection for an electromagnetic (EM) solver for each of the one or more sub-zones. Embodiments may also include modeling each of the one or more sub-zones.