公开(公告)号：US20050041451A1

公开(公告)日：2005-02-24

申请号：US10940927

申请日：2004-09-15

Applicant: Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

Inventor： Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C19/08

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract translation: 诸如数据选通输入缓冲器或数据输入缓冲器的数据缓冲器，其可以以多种模式操作，例如单模（SM）和双模（DM），并且其中通过提供信号选择模式， 例如诸如地址信号或外部命令信号的外部信号。 一种可用于SM / DM两用的数据缓冲器，可以提高数据设置/保持余量。 一种包括上述数据缓冲器中的一个或多个的半导体存储器件。 一种用于控制传播延迟时间的方法，其可以改善SM / DM两用数据缓冲器中的数据建立/保持余量。

公开(公告)号：US06819602B2

公开(公告)日：2004-11-16

申请号：US10278071

申请日：2002-10-23

Applicant: Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

Inventor： Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

IPC: G11C700

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract translation: 诸如数据选通输入缓冲器或数据输入缓冲器的数据缓冲器，其可以以多种模式操作，例如单模（SM）和双模（DM），并且其中通过提供信号选择模式， 例如诸如地址信号或外部命令信号的外部信号。 一种可用于SM / DM两用的数据缓冲器，可以提高数据设置/保持余量。 一种包括上述数据缓冲器中的一个或多个的半导体存储器件。 一种用于控制传播延迟时间的方法，其可以改善SM / DM两用数据缓冲器中的数据建立/保持余量。

公开(公告)号：US06650594B1

公开(公告)日：2003-11-18

申请号：US10281342

申请日：2002-10-28

Applicant: Jung-Bae Lee ,  Dong-Yang Lee

Inventor： Jung-Bae Lee ,  Dong-Yang Lee

IPC: G11C800

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C7/22 ,  G11C7/222

Abstract: A semiconductor integrated circuit and a memory device capable of selecting power-down exit speed and power-save modes and method thereof are provided. The memory device includes a command decoder for generating a power-down signal in response to a power-down command, a mode register (MRS) for storing power-down exit information, a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal, and a controller for controlling the DLL or PLL circuit. At power-down exit of the memory device, the power-down exit information can be selected between a fast wakeup time and a slow wakeup time.

Abstract translation: 提供了能够选择掉电退出速度和省电模式的半导体集成电路和存储器件及其方法。 存储器件包括用于响应于掉电命令产生掉电信号的命令解码器，用于存储掉电退出信息的模式寄存器（MRS），诸如DLL或PLL电路的时钟同步电路，用于产生 与外部时钟信号同步的内部时钟信号，以及用于控制DLL或PLL电路的控制器。 在存储设备的掉电退出时，可以在快速唤醒时间和缓慢的唤醒时间之间选择掉电退出信息。

公开(公告)号：US06621371B2

公开(公告)日：2003-09-16

申请号：US09834512

申请日：2001-04-13

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: H03H738

CPC classification number: H03H11/30 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/14 ,  H05K2201/09263

Abstract: The present invention provides a system board and an impedance control method thereof. The board includes a plurality of modules or devices, and a control apparatus for controlling the modules or devices. Signal lines are connected from the control apparatus to the plurality of modules or devices and are arranged so that the length of the signal lines between the control apparatus and the plurality of modules or devices becomes shorter the distance from the control apparatus increases. Therefore, the present invention can reduce the signal distortion phenomenon by controlling the characteristic impedance of the signal lines between the control apparatus and the plurality of modules or devices such that the characteristic impedance decreases exponentially with increasing distance from the control apparatus in the case in which modules or devices are plugged into the system board.

Abstract translation: 本发明提供一种系统板及其阻抗控制方法。 该板包括多个模块或装置，以及用于控制模块或装置的控制装置。 信号线从控制装置连接到多个模块或装置，并且被布置成使得控制装置和多个模块或装置之间的信号线的长度在距控制装置的距离增加时变短。 因此，本发明可以通过控制控制装置与多个模块或装置之间的信号线的特性阻抗来减小信号失真现象，使得随着距离控制装置的距离的增加，特性阻抗随指数增加而降低 模块或设备插入系统板。

公开(公告)号：US06466071B2

公开(公告)日：2002-10-15

申请号：US09826566

申请日：2001-04-05

Applicant: Kyu-hyoun Kim ,  Jung-bae Lee

Inventor： Kyu-hyoun Kim ,  Jung-bae Lee

IPC: H03K3017

CPC classification number: H03K5/1565 ,  H03K5/133 ,  H03L7/0812 ,  H03L2207/12 ,  Y10S331/02

Abstract: A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.

Abstract translation: 通过延迟信号以产生信号的延迟版本并产生响应于信号从第一状态到第二状态的转变而从第一状态转变到第二状态的输出信号来对信号进行占空比校正， 将信号的延迟版本从第二状态转换到第一状态。 响应于信号从第二状态到第一状态的转变以及信号从第一状态到第二状态的延迟版本的转变，输出信号从第二状态转变到第一状态。

公开(公告)号：US06380799B1

公开(公告)日：2002-04-30

申请号：US09721130

申请日：2000-11-22

Applicant: Dae-hyun Chung ,  Jung-bae Lee

Inventor： Dae-hyun Chung ,  Jung-bae Lee

IPC: G05F110

CPC classification number: G05F1/56 ,  G06F1/26 ,  G11C5/14 ,  G11C11/407 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04

Abstract: An internal voltage generation circuit is provided which can stably generate an internal supply voltage even if an external supply voltage decreases. The internal voltage generation circuit includes first and second level shifters, a differential amplifier and a driver. The first level shifter is connected to an internal supply voltage terminal and lowers the internal supply voltage to a predetermined voltage level. The second level shifter is connected to a reference voltage terminal and lowers a reference voltage to a predetermined voltage level. The differential amplifier compares the output voltage of the second level shifter with the output voltage of the first level shifter and amplifies the difference between the two output voltages. The driver generates the internal supply voltage in response to the output of the differential amplifier. The first and second level shifters may be source followers that decrease the internal supply voltage and the reference supply voltage, respectively, by a threshold voltage. Accordingly, the internal voltage generation circuit may stably generate the internal supply voltage even if the level of the external supply voltage is lowered, and restores the level of the internal supply voltage to its original level equal to the reference voltage even when the level of the internal supply voltage drops.

Abstract translation: 提供内部电压产生电路，即使外部电源电压降低，也能够稳定地产生内部电源电压。 内部电压产生电路包括第一和第二电平移位器，差分放大器和驱动器。 第一电平移位器连接到内部电源电压端子，并将内部电源电压降低到预定电压电平。 第二电平移位器连接到参考电压端子并将参考电压降低到预定电压电平。 差分放大器将第二电平移位器的输出电压与第一电平移位器的输出电压进行比较，并放大两个输出电压之间的差值。 驱动器响应差分放大器的输出产生内部电源电压。 第一和第二电平移位器可以是分别通过阈值电压将内部电源电压和参考电源电压降低的源极跟随器。 因此，即使外部电源电压的电平降低，内部电压产生电路也可以稳定地产生内部电源电压，并且即使当内部电源电平的电平等于参考电压时也将内部电源电压的电平恢复到其原始电平 内部电源电压下降。

公开(公告)号：US06240039B1

公开(公告)日：2001-05-29

申请号：US09524037

申请日：2000-03-13

Applicant: Jung-bae Lee ,  Chul-woo Yi

Inventor： Jung-bae Lee ,  Chul-woo Yi

IPC: G11C800

CPC classification number: G11C8/10

Abstract: A semiconductor memory device is provided having reduced power consumption during a normal operation. The semiconductor memory device includes a sub word-line defined by segmenting a word-line and a driving signal generator for selectively driving the sub word-line according to a column address. The driving signal generator is controlled by a selection signal corresponding to the column address and a mode signal for specifying an operation mode of the semiconductor memory device. The semiconductor memory device enables part of the word-line according to the column address. The semiconductor memory device using a sub word-line driver to reduce the number of memory cells which are sensed, thereby reducing power consumption.

Abstract translation: 提供半导体存储器件，其在正常操作期间具有降低的功耗。 半导体存储器件包括通过分割字线定义的子字线和用于根据列地址选择性地驱动子字线的驱动信号发生器。 驱动信号发生器由对应于列地址的选择信号和用于指定半导体存储器件的操作模式的模式信号控制。 半导体存储器件根据列地址使得字线的一部分成为可能。 使用子字线驱动器的半导体存储器件减少感测的存储器单元的数量，从而降低功耗。

公开(公告)号：US06232812B1

公开(公告)日：2001-05-15

申请号：US09196994

申请日：1998-11-20

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: H03H1126

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03K5/133 ,  H03L7/0814 ,  H03L7/091

Abstract: Programmable delay lines include a delay circuit having an input and a plurality of outputs which each provide a respective delayed version of a periodic input signal provided to the input. A delay switch is also provided to pass at least one of the plurality of outputs of the delay circuit to a switch output, in response to a digital control signal (P1-Pn). A preferred phase comparing circuit is also provided. This phase comparing circuit compares the input signal against the delayed versions of the input signal (at the plurality of outputs) and generates a digital phase signal (F1-Fn) that identifies which of the delayed versions of the input signal is in-phase with the input signal. The programmable delay line also includes a pointer which generates the digital control signal in response to the digital phase signal and a plurality of pointer control signals (S0, S1 and WS).

Abstract translation: 可编程延迟线包括具有输入和多个输出的延迟电路，每个输出提供提供给输入的周期性输入信号的相应延迟版本。 还提供延迟开关以响应于数字控制信号（P1-Pn）将延迟电路的多个输出中的至少一个输出传递到开关输出。 还提供了优选的相位比较电路。 该相位比较电路将输入信号与输入信号的延迟版本（在多个输出端）进行比较，并产生数字相位信号（F1-Fn），该数字相位信号识别输入信号的延迟版本中的哪一个与 输入信号。 可编程延迟线还包括响应于数字相位信号和多个指针控制信号（S0，S1和WS）产生数字控制信号的指针。

公开(公告)号：US6154416A

公开(公告)日：2000-11-28

申请号：US409178

申请日：1999-09-30

Applicant: Jung-bae Lee ,  Si-yeol Lee

Inventor： Jung-bae Lee ,  Si-yeol Lee

IPC: G11C11/413 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/785 ,  G11C11/4087 ,  G11C7/1006 ,  G11C8/00

Abstract: A column address decoder for two bit prefetch of a semiconductor device and a decoding method thereof are provided. The column address decoder includes a memory cell array having a plurality of memory cells for storing data and redundancy memory cells for replacing poor memory cells, a plurality of bit lines connected to the memory cells, a plurality of input and output lines, a plurality of switching means connected between the bit lines and the input and output lines. It also includes an even predecoder for receiving the less significant bits of the address received as input from the outside and predecoding the less significant bits in which the least significant bit is `0` of the less significant bits, an inverting decoder for reproducing the less significant bits of the external address corresponding to the address predecoded by the even predecoder, and a redundancy enable signal generating portion for generating a redundancy enable signal for receiving the output of the inverting decoder and activating one of the redundancy memory cells. According to the present invention, the data processing speed of the semiconductor memory device is increased.

Abstract translation: 提供了一种用于半位装置的两位预取的列地址解码器及其解码方法。 列地址解码器包括存储单元阵列，具有用于存储数据的多个存储单元和用于替换不良存储单元的冗余存储单元，连接到存储单元的多个位线，多个输入和输出线， 连接在位线和输入和输出线之间的开关装置。 它还包括一个偶数预解码器，用于从外部接收作为输入接收的地址的较低有效位，并对较低有效位进行预编码，其中最低有效位是较低有效位的“0”，用于再现较少有效位的反相解码器 对应于由偶数预解码器预解码的地址的外部地址的有效位，以及冗余使能信号产生部分，用于产生用于接收反相解码器的输出并激活冗余存储单元之一的冗余使能信号。 根据本发明，半导体存储器件的数据处理速度提高。

公开(公告)号：US6147527A

公开(公告)日：2000-11-14

申请号：US136871

申请日：1998-08-19

Applicant: Jung-Bae Lee ,  Sung-Geun Lee ,  Jing-Man Han

Inventor： Jung-Bae Lee ,  Sung-Geun Lee ,  Jing-Man Han

IPC: G11C11/407 ,  G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087 ,  H04L7/033 ,  H03K5/14

CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/133 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0337

Abstract: An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.

Abstract translation: 内部时钟发生器，其包括插入在数字延迟锁定环和外部产生的时钟信号之间的开关控制器。 当外部时钟和内部时钟同相时，开关控制器可以从下一个周期开始降低电流消耗。 此外，当外部时钟和内部时钟同相时，不必要元件的驱动被抑制，从而降低了内部时钟发生器的电流消耗。