公开(公告)号：US20020126028A1

公开(公告)日：2002-09-12

申请号：US10024466

申请日：2001-12-17

Applicant: STMicroelectronics S.r.I.

Inventor： Sandro Dalle Feste ,  Nadia Serina ,  Giovanni Cesura ,  Marco Bianchessi

IPC: H03M001/10

CPC classification number: H03M3/344 ,  H03M3/46

Abstract: A test signal with given spectral characteristics is injected at input to the quantizer stage of the converter. The same test signal is subjected to cross-correlation with a given signal so as to generate coefficients used for filtering the quantization noise converted into digital form. In this way, a compensation signal is obtained that is applied to the output signal of the quantizer stage jointly with a first compensation signal obtained by applying, to the quantization noise converted into digital form, the same transfer function 28) of the converter. In this way a signal is obtained which, in addition to being used as the global output signal of the converter, is also used for the aforesaid operation of cross-correlation with the test signal.

Abstract translation: 具有给定频谱特性的测试信号在输入端被注入到转换器的量化器级。 相同的测试信号经受与给定信号的互相关，以便产生用于滤波转换为数字形式的量化噪声的系数。 以这种方式，获得补偿信号，该补偿信号与通过将转换成数字形式的量化噪声相同的传递函数28获得的第一补偿信号一起应用于量化器级的输出信号。 以这种方式，获得了除了用作转换器的全局输出信号之外，还用于上述与测试信号互相关的操作的操作的信号。

公开(公告)号：US20020125582A1

公开(公告)日：2002-09-12

申请号：US10037485

申请日：2001-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684

Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations. In addition, the areas where the two wafers are made may be separate, and the interconnection structures may be made with materials incompatible with silicon processing, without any risk of contamination.

Abstract translation: 一种用于制造集成器件的方法包括以下步骤：在半导体材料的第一晶片中形成包括半导体区域和隔离区域的集成结构; 在半导体材料的第二晶片上形成包括具有能够与第一晶片的半导体区域反应的金属材料的至少一个结合区域的插塞元件的金属材料的互连结构; 以及通过使所述插塞元件的接合区域与所述半导体区域直接反应从而形成金属硅化物，将所述第一和第二晶片接合在一起。 因此，用于形成互连结构的冶金操作完全独立于处理硅所需的操作，使得在两组操作之间不存在任何干扰。 此外，制造两个晶片的区域可以是分开的，并且互连结构可以由与硅加工不相容的材料制成，而没有任何污染的风险。

公开(公告)号：US20020123160A1

公开(公告)日：2002-09-05

申请号：US10055029

申请日：2002-01-22

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo

IPC: H01L021/66

CPC classification number: H01L23/5225 ,  H01L23/481 ,  H01L23/60 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/074 ,  H01L29/0657 ,  H01L2223/6622 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The integrated semiconductor device includes a first chip of semiconductor material having first, high-voltage, regions at a first high-value voltage; a second chip of semiconductor material having second high-voltage regions connected to the first voltage; and a third chip of semiconductor material arranged between the first chip and the second chip and having at least one low-voltage region at a second, low-value, voltage. A through connection region is formed in the third chip and is connected to the first and second high-voltage regions; through insulating regions surround the through connection region and insulate it from the low-voltage region.

Abstract translation: 集成半导体器件包括具有第一高电压值的第一高电压区域的半导体材料的第一芯片; 具有连接到第一电压的第二高电压区域的第二半导体材料芯片; 以及布置在所述第一芯片和所述第二芯片之间并且具有第二低电压值的至少一个低电压区域的半导体材料的第三芯片。 在第三芯片中形成贯通连接区域并连接到第一和第二高压区域; 通过绝缘区域围绕通过连接区域并将其与低电压区域绝缘。

公开(公告)号：US20020109931A1

公开(公告)日：2002-08-15

申请号：US10001922

申请日：2001-11-13

Applicant: STMicroelectronics S.r.I.

Inventor： Benedetto Vigna ,  Simone Sassolini ,  Sarah Zerbini ,  Lorenzo Baldo

IPC: G11B005/596

CPC classification number: G01R33/0286 ,  G11B5/59677

Abstract: Described herein is a read/write transducer for a hard disk drivewith dual actuation stage, comprising at least one hard disk and at least one suspension carrying the read/write transducer. The read/write transducer comprises a supporting body having a substantially parallelepipedal shape, a read/write head arranged on a front face of the supporting body, and a grating defined on one of the side faces of the supporting body during the process of manufacture of the read/write transducer. The grating enables measurement of the position of the read/write transducer with respect to the corresponding suspension in an optical way using a laser transmitter emitting and directing towards the grating a laser beam, and a laser receiver arranged to intercept the laser beam reflected by the grating and outputting a position signal on the basis of which it is possible to calculate, in a simple way, the position of the read/write transducer with respect to the corresponding suspension.

Abstract translation: 这里描述了一种用于具有双驱动级的硬盘驱动器的读/写换能器，包括至少一个硬盘和至少一个承载读/写换能器的悬架。 读/写换能器包括具有基本上平行六面体形状的支撑体，布置在支撑体的前表面上的读/写头和在制造过程中在支撑体的一个侧面上限定的光栅 读/写传感器。 该光栅能够使用激光发射器以光学方式测量读/写换能器相对于相应悬架的位置，该激光发射器向激光束发射和指向光栅;以及激光接收器，被布置成拦截由 光栅并输出位置信号，基于此可以以简单的方式计算读/写换能器相对于相应悬架的位置。

公开(公告)号：US20020097071A1

公开(公告)日：2002-07-25

申请号：US10032232

申请日：2001-12-21

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Angelo Nagari ,  Germano Nicollini

IPC: H03B001/00

CPC classification number: G11C7/1051 ,  H03K19/00361

Abstract: The buffer has an output stage formed by two complementary MOS transistors connected so as to operate in phase opposition between the supply terminals and two driver stages having the input in common. Each driver stage has a first branch comprising a current-generator connected between the gate electrode of the transistor to be driven and a supply terminal and an electronic switch controlled by the input and connected between the same gate electrode and the other supply terminal, and a second branch which comprises, connected in series, a transistor connected as a diode and an electronic switch controlled by the output, and is arranged between the gate electrode of the transistor to be driven and a respective supply terminal. The buffer can control a load with a constant switching current, is simple in structure, and occupies a small area.

Abstract translation: 缓冲器具有由两个互补MOS晶体管形成的输出级，所述两个互补MOS晶体管被连接以在电源端子和具有共同输入的两个驱动器级之间相对操作。 每个驱动器级具有第一分支，包括连接在待驱动晶体管的栅电极与供电端子之间的电流发生器和由输入控制并连接在同一栅电极和另一供电端子之间的电子开关， 第二分支，其包括串联连接的二极管的晶体管和由输出控制的电子开关，并且被布置在待驱动的晶体管的栅电极和相应的供电端子之间。 缓冲器可以用恒定的开关电流来控制负载，结构简单，占用面积小。

公开(公告)号：US20020093120A1

公开(公告)日：2002-07-18

申请号：US10036335

申请日：2001-12-26

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Magni ,  Andrea Cigada

IPC: B29C033/00

CPC classification number: H01L21/565 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method is for forming a plastic protective package for an electronic device integrated on a semiconductor and comprising an electronic circuit to be encapsulated in the protective package. The electronic device may be at least partially activated from outside of the protective package. The method may include providing a mold having a half-mold with an insert abutting towards the inside of the mold and an end having an element that can be elastically deformed to abut in pressing contact against at least one portion of the integrated circuit. The method may also include injecting a resin into the mold so that the protective package has a hole by the at least one portion of the electronic circuit.

Abstract translation: 一种用于形成用于集成在半导体上的电子器件的塑料保护封装件的方法，包括要封装在保护封装中的电子电路。 电子设备可以至少部分地从保护包装的外部激活。 该方法可以包括提供具有半模的模具，其具有与模具内部邻接的插入件，端部具有能够弹性变形以抵抗与集成电路的至少一部分压接的元件。 该方法还可以包括将树脂注入到模具中，使得保护包装件通过电子电路的至少一部分具有孔。

公开(公告)号：US20020087817A1

公开(公告)日：2002-07-04

申请号：US09977561

申请日：2001-10-15

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Tomaiuolo ,  Salvatore Nicosia ,  Luigi Pascucci

IPC: G06F012/00

CPC classification number: G11C7/1033 ,  G11C7/1045

Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

Abstract translation: 多用途隔行存储器件具有两种不同的同步和异步模式。 存储器使用用于检测地址转换的电路，用作系统的同步时钟，以通过使当前输入的外部地址与存储在地址计数器中的当前输入的外部地址进行比较来使存储器件的控制电路识别所需的访问模式 的两行记忆体。 存储装置包括用于输出数据的缓冲器。 缓冲器包括用于将输出节点预充电到对应于两个可能逻辑状态的电压之间的中间电压的电路，从而降低噪声并改善传输时间。

公开(公告)号：US20020080658A1

公开(公告)日：2002-06-27

申请号：US09996082

申请日：2001-11-28

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Tiziana Signorelli ,  Francesco Pulvirenti ,  Calogero Ribellino

IPC: G11C007/00

CPC classification number: G06F11/006 ,  H01L2223/5444

Abstract: A circuit architecture and a method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture includes at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a circuit (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from a normal mode over to a trimming mode. This circuit architecture further includes a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing the non-volatile memory (3) state at power-on or at a simulating phase, and storing the sequence (25) of trimming data at a programming phase; an interface (6) is provided between the first multifunctional input pin (8), the second multifunctional input pin (9), and the additional access pin (7), the at least one non-volatile memory unit (3), and the volatile memory unit (2), for initially storing the sequence of trimming data (25) into the volatile memory unit (2) and subsequently timing the trimming operation.

Abstract translation: 一种用于在应用板上直接执行修整操作或者在封装集成电子设备之后进行修整操作的电路架构和方法。 电路架构包括至少一个具有非易失性存储元件（5）的非易失性存储器单元（3）和用于修改存储元件（5）的状态的电路（17,19），第一多功能输入引脚 8），其中接收到修剪数据的序列（25），其中接收到修剪操作的定时信号的第二多功能输入引脚（9）和用于将电路架构操作从正常切换的附加接入引脚（7） 模式切换到修剪模式。 该电路架构还包括与非易失性存储器单元（3）相关联的易失性存储器单元（2），用于在通电或模拟阶段存储非易失性存储器（3）状态，并存储序列（25 ）在编程阶段修剪数据; 在第一多功能输入引脚（8），第二多功能输入引脚（9）和附加存取引脚（7）之间提供接口（6），所述至少一个非易失性存储单元（3）和 易失性存储器单元（2），用于初始将修整数据（25）的序列存储到易失性存储器单元（2）中，并且随后对修整操作进行定时。

公开(公告)号：US20020073347A1

公开(公告)日：2002-06-13

申请号：US09982132

申请日：2001-10-16

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Zafarana ,  Claudia Castelli

IPC: G06F001/26

CPC classification number: G06F1/26 ,  Y10T307/505 ,  Y10T307/555

Abstract: A managing system manages a plurality of VRMs associated with a plurality of microprocessors and connected in parallel together between first and second voltage references, the VRMs having output terminals connected together and arranged to communicate over a common bus. The managing system includes an error amplifier being input an output voltage signal from the VRM plurality, a reference voltage, and a droop voltage produced through an equivalent droop resistor receiving an output current signal from the VRM plurality and being connected to the common bus. The error amplifier effects a comparison of the input signals to generate a control voltage signal to the VRM plurality. Advantageously, the managing system comprises a controller connected to the equivalent droop resistor.

Abstract translation: 管理系统管理与多个微处理器相关联并且在第一和第二电压基准之间并联连接的多个VRM，所述VRM具有连接在一起的输出端子并被布置成通过公共总线进行通信。 管理系统包括误差放大器，其输入来自VRM多个的输出电压信号，参考电压以及通过从VRM多路复用并连接到公共总线的等效下降电阻产生的下降电压。 误差放大器对输入信号进行比较，以产生对VRM多个的控制电压信号。 有利地，管理系统包括连接到等效下降电阻器的控制器。

公开(公告)号：US20020063648A1

公开(公告)日：2002-05-30

申请号：US09972751

申请日：2001-10-05

Applicant: STMicroelectronics S.r.I.

Inventor： Cristiano Meroni ,  Edoardo Botti ,  Andrea Baschirotto ,  Massimo Ghioni

IPC: H03M001/66

CPC classification number: H03M1/0682 ,  H03M1/0665 ,  H03M1/74

Abstract: A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index corresponding to the sign of the input code; activating a first set of positive generator elements and a second set of negative generator elements, the number of the positive generator elements activated and the number of the negative generator elements activated being equal to one another and proportional to the input code, and the addresses of the positive generator elements activated and of the negative generator elements activated being a function of the selected index; generating the first output analog signal by summing the positive elementary contributions supplied by the positive generator elements activated, and generating the second output analog signal by summing the negative elementary contributions supplied by the negative generator elements activated; and updating the selected index according to the input code.