公开(公告)号：US20170083474A1

公开(公告)日：2017-03-23

申请号：US14862011

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Yasuko Eckert ,  Kapil Dev ,  John Kalamatianos ,  Indrani Paul

IPC: G06F13/42 ,  G06F13/18 ,  G06F12/08

CPC classification number: G06F13/4234 ,  G06F12/084 ,  G06F12/0862 ,  G06F13/18 ,  G06F2212/314 ,  G06F2212/603 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A plurality of first controllers operate according to a plurality of access protocols to control a plurality of memory modules. A second controller receives access requests that target the plurality of memory modules and selectively provides the access requests and control information to the plurality of first controllers based on physical addresses in the access requests. The second controller generates the control information for the first controllers based on statistical representations of the access requests to the plurality of memory modules.

公开(公告)号：US20170083444A1

公开(公告)日：2017-03-23

申请号：US14862030

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kapil Dev ,  Mitesh R. Meswani ,  David A. Roberts ,  Yasuko Eckert ,  Indrani Paul ,  John Kalamatianos

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0871 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/2515 ,  G06F2212/502 ,  G06F2212/601

Abstract: A cache controller to configure a portion of a first memory as cache for a second memory responsive to an indicator of locality of memory access requests to the second memory. The indicator of locality determines a probability that a location of a memory access request to the second memory is predictable based upon at least one previous memory access request. The cache controller may determine a size of the cache based on a value of the indicator of locality or modify the size of the cache in response to changes in the value of the indicator of locality.

公开(公告)号：US09058278B2

公开(公告)日：2015-06-16

申请号：US13720072

申请日：2012-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Paul Keltcher

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A method, an apparatus, and a non-transitory computer readable medium for tracking accuracy and coverage of a prefetcher in a processor are presented. A table is maintained and indexed by an address, wherein each entry in the table corresponds to one address. A number of demand requests that hit in the table on a prefetch, a total number of demand requests, and a number of prefetch requests are counted. The accuracy of the prefetcher is calculated by dividing the number of demand requests that hit in the table on a prefetch by the number of prefetch requests. The coverage of the prefetcher is calculated by dividing the number of demand requests that hit in the table on a prefetch by the total number of demand requests. The table and the counters are reset when a reset condition is reached.

Abstract translation: 提出了一种用于跟踪处理器中的预取器的精度和覆盖率的方法，装置和非暂时计算机可读介质。 表由地址维护和索引，其中表中的每个条目对应于一个地址。 对预取中的表中的一些需求请求，需求请求的总数以及预取请求的数量进行计数。 通过将预取中的表中命中的请求请求数除以预取请求数来计算预取器的准确性。 预取器的覆盖率是通过将预取中的表中命中的请求请求数除以请求请求总数来计算的。 当达到复位条件时，表和计数器被复位。

公开(公告)号：US20140297965A1

公开(公告)日：2014-10-02

申请号：US13854541

申请日：2013-04-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ramkumar Jayaseelan ,  John Kalamatianos

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/528 ,  G06F11/366 ,  G06F12/0215 ,  G06F12/0891

Abstract: A processor employs a prefetch prediction module that predicts, for each prefetch request, whether the prefetch request is likely to be satisfied from (“hit”) the cache. The arbitration priority of prefetch requests that are predicted to hit the cache is reduced relative to demand requests or other prefetch requests that are predicted to miss in the cache. Accordingly, an arbiter for the cache is less likely to select prefetch requests that hit the cache, thereby improving processor throughput.

Abstract translation: 处理器采用预取预测模块，其针对每个预取请求预测预取请求是否可能从缓存（“命中”）满足。 预测到达高速缓存的预取请求的仲裁优先级相对于预期在高速缓存中丢失的请求请求或其他预取请求而减少。 因此，缓存的仲裁器不太可能选择命中高速缓存的预取请求，从而提高处理器的吞吐量。