公开(公告)号：US10388754B2

公开(公告)日：2019-08-20

申请号：US15343776

申请日：2016-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.

公开(公告)号：US10361311B2

公开(公告)日：2019-07-23

申请号：US15825409

申请日：2017-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L21/321 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

公开(公告)号：US10276442B1

公开(公告)日：2019-04-30

申请号：US15993017

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Adra Carr ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A first field-effect transistor has a first source/drain region, and a second field-effect transistor has a second source/drain region. A first silicide layer is arranged to wrap around the first source/drain region, and a second silicide layer is arranged to wrap around the second source/drain region. The first silicide layer contains a first metal, and the second silicide layer contains a second metal different from the first metal.

公开(公告)号：US10236363B2

公开(公告)日：2019-03-19

申请号：US15458457

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/324 ,  H01L29/417 ,  H01L29/78 ,  H01L29/10

Abstract: Device structures and fabrication methods for a vertical field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A first spacer layer is formed on the first source/drain region. A dielectric layer is formed that extends in the vertical direction from the first spacer layer to a top surface of the semiconductor fin. The dielectric layer is recessed in the vertical direction, and a second spacer layer is formed on the recessed dielectric layer such that the dielectric layer is located in the vertical direction between the first spacer layer and the second spacer layer. After the dielectric layer is removed to open a space between the first spacer layer and the second spacer layer, a gate electrode is formed in the space. The vertical field-effect transistor has a gate length that is equal to a thickness of the recessed dielectric layer.

公开(公告)号：US10229987B2

公开(公告)日：2019-03-12

申请号：US15815857

申请日：2017-11-17

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267

Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.

公开(公告)号：US10217672B2

公开(公告)日：2019-02-26

申请号：US15889654

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

IPC: H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088

Abstract: A device includes, among other things, a first vertical transistor device positioned above a semiconductor substrate. The first vertical transistor device includes a first gate structure, a first top spacer positioned above the first gate structure and having a first thickness in a vertical direction, and a first doped top source/drain structure positioned above the first top spacer. A second vertical transistor device positioned above the semiconductor substrate includes a second gate structure, a second top spacer positioned above the second gate structure and having a second thickness in a vertical direction less than the first thickness, and a second doped top source/drain structure positioned above the second top spacer.

公开(公告)号：US10199480B2

公开(公告)日：2019-02-05

申请号：US15280451

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Tenko Yamashita ,  Kangguo Cheng ,  Chun-Chen Yeh

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/033 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height. The method further includes forming a top source/drain layer over the vertical channel, replacing the dummy gate with a metal gate, and forming self-aligned source, drain and gate contacts.

公开(公告)号：US10199220B2

公开(公告)日：2019-02-05

申请号：US15652413

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US10170583B2

公开(公告)日：2019-01-01

申请号：US15244067

申请日：2016-08-23

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.

公开(公告)号：US10170319B2

公开(公告)日：2019-01-01

申请号：US15227142

申请日：2016-08-03

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/283 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L21/768

Abstract: A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.