公开(公告)号：US10276683B2

公开(公告)日：2019-04-30

申请号：US15718958

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Jinping Liu ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/40 ,  H01L29/47 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8238

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include a semiconductor substrate having an n-FET region and a p-FET region each having source/drain regions; a titanium silicon (Ti—Si) intermix phase Ti liner on an upper surface of the n-FET region source/drain regions; and titanium silicide (TiSi) forming an upper surface of the p-FET region source/drain regions.

公开(公告)号：US20190123162A1

公开(公告)日：2019-04-25

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US10269983B2

公开(公告)日：2019-04-23

申请号：US15590409

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L29/41

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.

公开(公告)号：US10263099B2

公开(公告)日：2019-04-16

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/51

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US10249535B2

公开(公告)日：2019-04-02

申请号：US15433188

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Chanemougame ,  Lars Liebmann ,  Nigel Cave

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/78

Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

公开(公告)号：US20190096677A1

公开(公告)日：2019-03-28

申请号：US15712301

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.

公开(公告)号：US10243053B1

公开(公告)日：2019-03-26

申请号：US15876316

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Chanro Park

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/417 ,  H01L21/28 ,  H01L23/528 ,  H01L29/78

Abstract: One illustrative IC product disclosed herein includes a gate structure for a transistor, a conductive source/drain contact structure and an insulating source/drain cap structure positioned above the conductive source/drain contact structure, wherein the insulating source/drain cap structure has a first notch formed therein. In one illustrative example, the product also includes a sidewall spacer that has a second notch in an upper portion of the sidewall spacer, wherein a first portion of the insulating source/drain cap structure is positioned in the second notch, and a conductive gate contact structure comprising first and second portions, the first portion of the conductive gate contact structure being positioned in the first notch and the second portion of the conductive gate contact structure being in contact with the gate structure.

公开(公告)号：US10236292B1

公开(公告)日：2019-03-19

申请号：US16156082

申请日：2018-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L29/786

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

公开(公告)号：US10236291B2

公开(公告)日：2019-03-19

申请号：US15801023

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/32 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US20190081145A1

公开(公告)日：2019-03-14

申请号：US15701678

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Nigel G. Cave ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A structure and method for forming sets of contact structures to source/drain regions of complimentary N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The structure including a NFET structure including a first fin positioned on a substrate and a PFET structure including a second fin positioned on the substrate, wherein a source/drain region (S/D) of the first fin and a S/D of the second fin include non-uniform openings at an uppermost surface. A method of forming non-uniformly openings in the S/Ds of the complimentary NFETs and PFETs including forming mask on the PFET to protect the structure during formation of openings in the NFET S/D. A method of forming non-uniform openings in the S/D of the complimentary NFETs and PFETs including reducing the epitaxially growth of the NFET S/D to form an opening therein.