公开(公告)号：US10096607B1

公开(公告)日：2018-10-09

申请号：US15603572

申请日：2017-05-24

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Robert R. Robison ,  Reinaldo Vega ,  Rajasekhar Venigalla

IPC: H01L29/78 ,  H01L27/11 ,  H01L21/84 ,  H01L21/822 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786

Abstract: A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.

公开(公告)号：US20180239016A1

公开(公告)日：2018-08-23

申请号：US15962418

申请日：2018-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Li-Wen Hung ,  Reinaldo Vega

IPC: G01S15/04 ,  H04B11/00 ,  G01S15/74

CPC classification number: G01S15/04 ,  G01S15/74 ,  H04B11/00

Abstract: A system and method are provided. The system includes a data reader having a processor for performing a signal frequency analysis, an ultrasound transmitter for transmitting ultrasound signals, and an ultrasound receiver for receiving reflected ultrasound signals. The system further includes a movable reflector for receiving the ultrasound signals and reflecting the ultrasounds signals back to the ultrasound receiver (a) as the reflected ultrasound signals without modulation when the movable reflector is stationary and (b) as the reflected ultrasound signals with modulation when the movable reflector is mobile. The system also includes a chip for storing a specification of motion states for the movable reflector.

公开(公告)号：US09728466B1

公开(公告)日：2017-08-08

申请号：US15140763

申请日：2016-04-28

Applicant: International Business Machines Corporation

Inventor： Hari V. Mallela ,  Robert R. Robison ,  Reinaldo Vega ,  Rajasekhar Venigalla

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/80 ,  H01L29/94 ,  H01L21/285 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/41741 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/78696

Abstract: Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.

公开(公告)号：US09312185B2

公开(公告)日：2016-04-12

申请号：US14270791

申请日：2014-05-06

Applicant: International Business Machines Corporation

Inventor： Cung Tran ,  Emre Alptekin ,  Viraj Sardesai ,  Reinaldo Vega

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/32 ,  H01L29/49 ,  H01L29/45 ,  H01L21/3105 ,  H01L49/02 ,  H01L23/525 ,  H01L21/285

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/32 ,  H01L21/76897 ,  H01L21/823443 ,  H01L23/5228 ,  H01L23/5256 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof.

Abstract translation: 本发明的实施例提供一种形成金属电阻器的方法。 该方法包括在替代金属栅极工艺中在半导体衬底的顶部上形成第一和第二结构，以分别具有与牺牲栅极的侧壁相邻的牺牲栅极和间隔物; 用蚀刻停止掩模覆盖第二结构; 用替换金属浇口代替第一结构的牺牲栅极; 去除蚀刻停止掩模以暴露第二结构的牺牲栅极; 在第二结构中形成作为金属电阻器的硅化物; 并形成与硅化物的接触。 在一个实施例中，形成硅化物包括硅化第二结构的牺牲栅极的顶部以形成金属电阻器。 在另一个实施例中，形成硅化物包括去除第二结构的牺牲栅极以暴露其下方的沟道区域并硅化。

公开(公告)号：US09082851B2

公开(公告)日：2015-07-14

申请号：US14087655

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Ravikumar Ramachandran ,  Henry K. Utomo ,  Reinaldo Vega

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A FinFET device which includes: a semiconductor substrate; a three dimensional fin oriented perpendicularly to the semiconductor substrate; a local trench isolation between the three dimensional fin and an adjacent three dimensional fin; a nitride layer on the local trench isolation; a gate stack wrapped around a central portion of the three dimensional fin and extending through the nitride layer; sidewall spacers adjacent to the gate stack and indirectly in contact with the nitride layer, two ends of the three dimensional fin extending from the sidewall spacers, a first end being for the source of the FET device and a second end being for a drain of the FET device; and an epitaxial layer covering each end of the three dimensional fin and being on the nitride layer. Also disclosed is a method of fabricating a FinFET device.

Abstract translation: 一种FinFET器件，包括：半导体衬底; 垂直于半导体衬底取向的三维鳍片; 三维翅片与相邻三维翅片之间的局部沟槽隔离; 局部沟槽隔离上的氮化物层; 围绕三维翅片的中心部分并延伸穿过氮化物层的栅极堆叠; 与栅叠层相邻并间接地与氮化物层接触的侧壁间隔件，三维鳍片的两端从侧壁间隔件延伸，第一端用于FET器件的源极，第二端用于漏极 FET器件; 以及覆盖三维翅片的每一端并且在氮化物层上的外延层。 还公开了一种制造FinFET器件的方法。

公开(公告)号：US20150108590A1

公开(公告)日：2015-04-23

申请号：US14059842

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Hari V. Mallela ,  Reinaldo Vega

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/772

CPC classification number: H01L21/28008 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/772

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.