公开(公告)号：US09905275B2

公开(公告)日：2018-02-27

申请号：US15434748

申请日：2017-02-16

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：US20170315734A1

公开(公告)日：2017-11-02

申请号：US15144141

申请日：2016-05-02

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

IPC: G06F3/06 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F9/4411 ,  G06F13/10 ,  G06F13/1668

Abstract: A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to detect a known state to enter based, at least in part, on communication with a host device, and reconfigure the memory device to prepare for the known state. A host controller is configured to communicate with the memory device to support a feature and protocol for detecting the known state for operation of the memory device. Related methods and systems are also disclosed.

公开(公告)号：US20170308382A1

公开(公告)日：2017-10-26

申请号：US15646874

申请日：2017-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G06F9/30 ,  G11C13/00 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10

CPC classification number: G06F9/30047 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1063 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2272

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

公开(公告)号：US09710192B2

公开(公告)日：2017-07-18

申请号：US15367631

申请日：2016-12-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0891

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/7203

Abstract: Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a first write command and may further be configured to cause the buffer to store the data in the array responsive, at least in part, to a flush command. The memory control unit may further be configured to interrupt the flush command to prepare for a read command or a second write command and resume the flush command once the read command or the second write command is performed.

公开(公告)号：US09696908B2

公开(公告)日：2017-07-04

申请号：US14980819

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G06F12/06 ,  G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  G11C16/10 ,  G11C16/32

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

公开(公告)号：US20150212738A1

公开(公告)日：2015-07-30

申请号：US14605593

申请日：2015-01-26

Applicant: Micron Technology, Inc.

Inventor： GIUSEPPE D'ELISEO ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

Abstract translation: 公开了用于在存储器中执行多个排队任务的方法和装置。 一个示例性设备包括被配置为耦合到主机的存储器。 存储器还被配置为从主机接收多个存储器访问请求，状态请求和执行命令，并且响应于来自主机的执行命令来执行多个存储器访问请求中的一个或多个。 执行命令包括与多个存储器访问请求的每个相应存储器访问请求对应的多个相应指示，并且指示主机是否请求存储器执行每个相应的存储器访问请求。

公开(公告)号：US20140281182A1

公开(公告)日：2014-09-18

申请号：US13838296

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Lucas Porzio

IPC: G06F3/06

CPC classification number: G06F13/1689 ,  G06F13/161 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

Abstract translation: 本文公开了用于可变延迟存储器操作的装置和方法。 示例性装置可以包括被配置为在第一寻址阶段期间接收指示命令类型的激活命令并在第二寻址阶段期间接收命令的存储器。 存储器还可以被配置为提供指示存储器不可用于执行命令的信息，所述信息至少部分地响应于在可变等待时间段期间接收命令并且提供指示存储器可用于执行命令的信息 至少部分地响应于在可变潜伏期之后接收命令。

公开(公告)号：US20140122814A1

公开(公告)日：2014-05-01

申请号：US13840929

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G06F9/30

CPC classification number: G06F9/30047 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1063 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2272

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

Abstract translation: 描述用于执行存储器操作的装置和方法。 示例性装置包括存储器操作控制器。 存储器操作控制器被配置为接收存储器指令并对其进行解码以提供用于对存储器指令执行存储器操作的内部信号。 存储器操作控制器还被配置为在可变等待时间周期期间提供指示存储器指令的可变等待时间周期的时间的信息。 在示例性方法中，在存储器处接收要写入数据的写指令和地址，并且提供指示用于写指令的可变等待时间周期结束的确认。 在确认之后等待可变总线周转后，接收写入指令的写入数据。