公开(公告)号：US20240087663A1

公开(公告)日：2024-03-14

申请号：US17944135

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： William Yu ,  Daniele Balluchi ,  Danilo Caraccio ,  Thomas T. Tangelder ,  Jacob S. Robertson ,  James G. Steele ,  Joemar Sinipete

IPC: G11C29/36 ,  G11C29/02 ,  G11C29/42

CPC classification number: G11C29/36 ,  G11C29/022 ,  G11C29/42 ,  G11C2029/3602

Abstract: Methods, systems, and devices related to built-in self-test (BIST) circuitry of a controller. The controller can be coupled to multiple memory devices. The BIST circuitry can include registers configured to store burst patterns. The BIST circuitry can perform a BIST operation on the memory devices contemporaneously and using the number of burst patterns.

公开(公告)号：US20240028249A1

公开(公告)日：2024-01-25

申请号：US17868286

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

公开(公告)号：US20230394155A1

公开(公告)日：2023-12-07

申请号：US17969916

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Alessandro Orlando ,  Craig A. Jones ,  Federica Cresci ,  Niccolò Izzo ,  Danilo Caraccio

IPC: G06F21/57 ,  G06F8/654 ,  G06F21/60 ,  H04L9/06

CPC classification number: G06F21/572 ,  G06F8/654 ,  G06F2221/033 ,  H04L9/0631 ,  G06F21/602

Abstract: Methods, systems, and devices related to field firmware update (FFU). A first memory of a memory module may receive an encrypted segment of a FW package associated with FFU. A decrypted segment of the FW package may be stored by the first memory. A re-encrypted segment of the FW package may be stored by the first memory. The re-encrypted segment of the FW package may be communicated to a second memory of the memory module.

公开(公告)号：US20230393780A1

公开(公告)日：2023-12-07

申请号：US17899900

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Niccolò Izzo ,  Danilo Caraccio

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/0664

Abstract: In some aspects, the techniques described herein relate to a device including: a datapath facilitating data transfers between a host device and a storage device; a firmware storage device storing a plurality of firmware tasks; and a processor, the processor including a hypervisor configured to: execute a given firmware task in the plurality of firmware tasks in a container, and control access to the datapath based on tags associated with instructions of the given firmware task.

公开(公告)号：US11720163B2

公开(公告)日：2023-08-08

申请号：US17870696

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/32 ,  G06F11/30 ,  G06F1/3234 ,  G06F13/16 ,  G11C5/14 ,  G06F1/30 ,  G06F1/3212 ,  G11C16/30 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/20

CPC classification number: G06F1/3275 ,  G06F1/305 ,  G06F1/3212 ,  G06F11/3062 ,  G06F13/1668 ,  G11C5/142 ,  G11C5/144 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/20 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US20230229560A1

公开(公告)日：2023-07-20

申请号：US17897037

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Angelo Visconti ,  Giorgio Servalli ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G06F11/14 ,  G06F12/06 ,  G06F11/10

CPC classification number: G06F11/1435 ,  G06F12/0646 ,  G06F11/1044 ,  G06F2212/1032 ,  G06F2201/805

Abstract: There are provided methods and systems for correcting an error from a memory. For example, there is provided a system for mitigating an error in a memory. The system can include a memory controller communicatively coupled to a host. The memory controller may be configured to receive information associated with a memory location. The information can indicate the error at the memory location. The controller may be configured to perform, upon receiving the information, certain operations. The operations can include copying data around the memory location, placing the copied data in a reserved area. And the operations can further include outputting, to a central controller, a set of physical addresses associated with the reserved area, wherein the central controller is configured to modify the set of physical address to conduct a data recovery off-line.

公开(公告)号：US20230096375A1

公开(公告)日：2023-03-30

申请号：US17489336

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Marco Sforzin ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.

公开(公告)号：US20230054662A1

公开(公告)日：2023-02-23

申请号：US17981703

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US11550678B2

公开(公告)日：2023-01-10

申请号：US17206881

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US11544201B2

公开(公告)日：2023-01-03

申请号：US17169042

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Danilo Caraccio ,  Angelo Alberto Rovelli

IPC: G06F12/1027 ,  G06F3/06 ,  G06F9/30 ,  G06F9/455

Abstract: Systems, apparatuses, and methods related to memory tracing in an emulated computing system are described. Static tracepoints can be inserted into a particular function as part of operating the emulated computing system. By executing the function including the static tracepoints as part of a memory access request, the emulated computing system can receive information corresponding to both a virtual address and a physical address in a real computing system in which data corresponding to the memory access request is stored.