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    Method of forming fins from different materials on a substrate
    143.
    发明授权
    Method of forming fins from different materials on a substrate 有权
    在基材上形成不同材料的翅片的方法

    公开(公告)号：US09396931B2

    公开(公告)日：2016-07-19

    申请号：US13956398

    申请日：2013-08-01

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

    IPC: H01L29/78 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

    Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

    Abstract translation: 形成不同材料的散热片的方法包括：提供具有顶表面的第一材料层的衬底，掩蔽衬底的第一部分，留下衬底的第二部分，蚀刻第二部分的第一开口，形成 在所述开口中的第二材料的主体到所述第一材料的所述层的顶表面的高度，去除所述掩模，以及在所述第一部分处形成所述第一材料的翅片，并在所述第二部分处形成所述第二材料的翅片 。 还公开了具有由至少两种不同材料形成的翅片的finFET器件。

    STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINES ON SEPARATE METAL LAYERS FOR INCREASED PERFORMANCE, AND RELATED METHODS
    144.
    发明申请
    STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINES ON SEPARATE METAL LAYERS FOR INCREASED PERFORMANCE, AND RELATED METHODS 有权
    静态随机访问存储器（SRAM）位元件，具有用于增加性能的单独金属层上的边界和相关方法

    公开(公告)号：US20160163713A1

    公开(公告)日：2016-06-09

    申请号：US14559205

    申请日：2014-12-03

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

    IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

    Abstract translation: 公开了在单独的金属层上具有字线的静态随机存取存储器（SRAM）位单元，以提高性能。 在一个方面，公开了采用第二金属层中的写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线增加宽度，这降低了字线电阻，减少了访问时间，并提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨迹。 为了将读取的字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在设置在第一金属层中的相应的轨道上。 对应于写入字线的着陆垫被放置在设置在第一金属层中的对应的轨道上。

    SHARED GLOBAL READ AND WRITE WORD LINES
    146.
    发明申请
    SHARED GLOBAL READ AND WRITE WORD LINES 有权
    共享全球阅读和写字线

    公开(公告)号：US20160141021A1

    公开(公告)日：2016-05-19

    申请号：US14546980

    申请日：2014-11-18

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

    Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

    MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS (ICs) EMPLOYING LOCAL INTERCONNECTS OF METAL LINES USING AN ELONGATED VIA, AND RELATED METHODS
    147.
    发明申请
    MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS (ICs) EMPLOYING LOCAL INTERCONNECTS OF METAL LINES USING AN ELONGATED VIA, AND RELATED METHODS 有权
    使用中断线（MOL）制造的集成电路（IC）使用延长线的金属线的本地互连及相关方法

    公开(公告)号：US20160079175A1

    公开(公告)日：2016-03-17

    申请号：US14484366

    申请日：2014-09-12

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong Zhu ,  Kern Rim ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang

    IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/53257 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.

    Abstract translation: 公开了采用使用细长通孔的金属线的局部互连的中线（MOL）制造的集成电路（IC）。 还公开了相关方法。 特别地，金属层中的不同金属线可能需要在IC的MOL工艺期间电连接。 在这方面，为了允许金属线互连，而不在例如在示例性方面中在印刷过程中难以提供的金属线上方提供这样的互连，在一个或多个金属线中提供细长或扩张的通孔 IC中的MOL层。 细长通道设置在MOL层中的金属层下方的MOL层中，并且延伸穿过MOL层的金属层中的两个或更多个相邻的金属层。 移动MOL层上方的互连可以简化IC的制造，特别是在纳米（nm）节点尺寸较小的情况下。

    THREE-PORT BIT CELL HAVING INCREASED WIDTH
    148.
    发明申请
    THREE-PORT BIT CELL HAVING INCREASED WIDTH 有权
    三端口单元有更大的宽度

    公开(公告)号：US20160064067A1

    公开(公告)日：2016-03-03

    申请号：US14468976

    申请日：2014-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C11/419 ,  H01L27/11 ,  H01L21/768 ,  H01L21/3213

    CPC classification number: G11C11/419 ,  G11C7/18 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C29/816 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/1104

    Abstract: An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm).

    Abstract translation: 一种装置包括第一读取端口，第二读取端口，写入端口和至少一个存储锁存器。 包括第一读取端口，第二读取端口和写入端口的位单元的宽度大于与位单元相关联的接触多边距（CPP）的两倍。 例如，位单元可以是与自对准双图案（SADP）工艺兼容的3端口静态随机存取存储器（SRAM）位单元，并且可以使用小于14纳米（nm）的半导体制造工艺来制造 ）。

    DUAL WRITE WORDLINE MEMORY CELL
    150.
    发明申请
    DUAL WRITE WORDLINE MEMORY CELL 有权
    双写WORDLINE MEMORY CELL

    公开(公告)号：US20150380080A1

    公开(公告)日：2015-12-31

    申请号：US14320024

    申请日：2014-06-30

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang

    IPC: G11C11/419 ,  G11C5/06

    CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

    Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

    Abstract translation: 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号而选择性地将位线耦合到第一逆变器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是独立可控的。

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