公开(公告)号：US20150092869A1

公开(公告)日：2015-04-02

申请号：US14507743

申请日：2014-10-06

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

IPC: H04L1/00 ,  H04L25/02

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D50/10

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Abstract translation: 一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。 发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定错误率对应的电压裕度来确定有线链路上的通信数据速率的范围。 通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

公开(公告)号：US20150089164A1

公开(公告)日：2015-03-26

申请号：US14386561

申请日：2012-12-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G06F13/42 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Abstract translation: 在允许每个等级的时钟分配树被允许在宽范围内漂移的多存储器存储器系统（例如，低功率存储器系统）中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错 排名适当地采样旨在该等级的命令，尽管有漂移。 执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。 本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。

公开(公告)号：US20150036732A1

公开(公告)日：2015-02-05

申请号：US14462561

申请日：2014-08-19

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

Abstract translation: 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号通过第一个alpha值进行调整，以得到第一个调整后的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择以确定接收到的数据值。

公开(公告)号：US20140337645A1

公开(公告)日：2014-11-13

申请号：US14445516

申请日：2014-07-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Jared L. Zerbe ,  Brian S. Leibowitz

IPC: G06F3/06 ,  G06F1/32 ,  G11C7/22

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2213/0038 ,  G11C5/14 ,  G11C5/148 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254

Abstract: A memory device is transitioned to a low-power mode in which an active-mode resource required to receive memory access commands from a memory controller at a first command-signaling frequency of the memory device is disabled. A first memory access command, transmitted by the memory controller, is received within the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract translation: 存储器件被转换到低功率模式，其中禁用在存储器设备的第一命令信号频率处从存储器控制器接收存储器访问命令所需的活动模式资源。 由存储器控制器发送的第一存储器访问命令在其中重新启用活动模式资源的过渡间隔期间使用备用信令资源在存储器设备内被接收。

公开(公告)号：US08855217B2

公开(公告)日：2014-10-07

申请号：US13633076

申请日：2012-10-01

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

IPC: H04B3/00 ,  H04L25/02 ,  H04L1/24 ,  H04L1/00 ,  H04L5/14 ,  H04L1/20

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D50/10

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Abstract translation: 一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。 发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定错误率对应的电压裕度来确定有线链路上的通信数据速率的范围。 通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

公开(公告)号：US20140237261A1

公开(公告)日：2014-08-21

申请号：US14133383

申请日：2013-12-18

Applicant: RAMBUS INC.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F12/14

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。

公开(公告)号：US20140173238A1

公开(公告)日：2014-06-19

申请号：US14098628

申请日：2013-12-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz ,  Pradeep Batra ,  Trung Am Diep

IPC: G06F12/14

CPC classification number: G06F21/85 ,  G06F21/78 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/065 ,  H04L9/12 ,  H04L2209/12 ,  H04L2209/56

Abstract: Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

Abstract translation: 描述了用于保护在存储器总线上共享并存储在存储器中的数据和指令的系统和方法。 用于写入和读取通道的独立且单独定时的流密码允许写入和读取事务之间的时序变化。 数据和指令可以在通道加密之前单独加密，以进一步保护信息。 垫片发生器和相关的加密电路被共享用于读取和写入数据，并且保护地址。 加密电路可以支持可变数据宽度，并且在一些实施例中，存储器设备包括可以使用重用存储器电路来实现共享密钥算法的安全电路。

公开(公告)号：US20140153631A1

公开(公告)日：2014-06-05

申请号：US13911363

申请日：2013-06-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。