公开(公告)号：US20160364641A1

公开(公告)日：2016-12-15

申请号：US15248167

申请日：2016-08-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tamae TAKANO ,  Nobuharu OHSAWA ,  Kiyoshi KATO

IPC: G06K19/077 ,  H01L27/28 ,  H01Q1/22 ,  G11C7/22 ,  H01Q1/36 ,  H01L51/05 ,  G11C7/06

CPC classification number: H01L27/13 ,  G06K19/07784 ,  G11C7/062 ,  G11C7/22 ,  H01F5/003 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/285 ,  H01L33/36 ,  H01L51/05 ,  H01L51/0591 ,  H01L51/5012 ,  H01L51/5203 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01Q1/2283 ,  H01Q1/36 ,  H01Q9/27 ,  Y10S257/922 ,  H01L2924/00

Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.

Abstract translation: 当在螺旋天线部分中设置占据大面积的导电层时，难以稳定地供电。 存储电路部分和螺旋天线部分通过堆叠在一起设置; 因此，可以防止电流流过占据存储电路部分中的大面积的导电层，从而可以实现省电。 此外，存储电路部分和盘绕天线部分通过堆叠在一起设置，因此可以有效地使用空间。 因此，可以实现小型化。

公开(公告)号：US20160163742A1

公开(公告)日：2016-06-09

申请号：US15016451

申请日：2016-02-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1156 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78645 ,  H01L29/7869 ,  H01L29/788

Abstract: A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the oxide layer, a second drain electrode layer in contact with the oxide layer, a gate insulating film in contact with the oxide layer, a first gate electrode layer overlapping with the source electrode layer and the first drain electrode layer and overlapping with a top surface of the oxide layer with the gate insulating film interposed therebetween, a second gate electrode layer overlapping with the source electrode layer and the second drain electrode layer and overlapping with the top surface of the oxide layer with the gate insulating film interposed therebetween, and a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween.

Abstract translation: 半导体器件包括氧化物层，与氧化物层接触的源极电极层，与氧化物层接触的第一漏极电极层，与氧化物层接触的第二漏极电极层，与氧化物层接触的栅极绝缘膜 所述氧化物层与所述源极电极层和所述第一漏极电极层重叠并与所述氧化物层的顶表面重叠的第一栅极电极层与所述栅极绝缘膜插入其间，与所述源极电极层重叠的第二栅电极层 所述第二漏极电极层与所述氧化物层的顶面重叠，并且所述栅极绝缘膜与所述第二漏极电极层重叠，并且所述第三栅极电极层与所述氧化物层的侧面重叠，并且所述栅极绝缘膜插入其间。

公开(公告)号：US20160149567A1

公开(公告)日：2016-05-26

申请号：US14945499

申请日：2015-11-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori MATSUZAKI ,  Kiyoshi KATO

IPC: H03K5/24

CPC classification number: H03K5/24 ,  G11C11/5642

Abstract: In a configuration including a first circuit for retaining a plurality of analog voltages and a second circuit capable of reading one of the analog voltages as a digital signal, correct data can be read even when characteristics of transistors in the first and second circuits vary with the temperature change. A reference voltage is applied to a gate of a transistor in the second circuit whose threshold voltage varies with the temperature change, and a corrected reference voltage is generated by adding a threshold voltage variation of the transistor in the second circuit to the reference voltage. An analog voltage is read out as a digital signal with the use of the corrected reference voltage, resulting in readout of correct data obtained by canceling out variations in characteristics due to the temperature change of the transistor in the first circuit.

Abstract translation: 在包括用于保持多个模拟电压的第一电路和能够读取模拟电压之一作为数字信号的第二电路的配置中，即使在第一和第二电路中的晶体管的特性随着 温度变化。 参考电压被施加到阈值电压随着温度变化而变化的第二电路中的晶体管的栅极，并且通过将第二电路中的晶体管的阈值电压变化与参考电压相加来产生校正的参考电压。 通过使用校正的参考电压将模拟电压作为数字信号读出，导致通过消除由于第一电路中的晶体管的温度变化引起的特性变化而获得的正确数据的读出。

公开(公告)号：US20150325599A1

公开(公告)日：2015-11-12

申请号：US14801936

申请日：2015-07-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Jun KOYAMA ,  Yutaka SHIONOIRI

IPC: H01L27/12 ,  H01L23/66 ,  H01L23/538 ,  H01L29/786

CPC classification number: H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

Abstract translation: 本发明提供一种处理器，其通过在对热敏感的基板（例如塑料基板或塑料膜基板）上形成使用多晶半导体的高功能集成电路。 此外，本发明提供一种无线发送和接收电力或信号的无线处理器，无线存储器及其信息处理系统。 根据本发明，一种信息处理系统包括一个元件形成区域，该元件形成区域包括晶体管，该晶体管至少具有由半导体膜形成的沟道形成区域，所述半导体膜片分隔成10至200nm的厚度的岛状物以及天线。 晶体管固定在柔性基板上。 其中形成包括元件形成区域的高功能集成电路并且半导体器件通过天线发送和接收数据的无线处理器。

公开(公告)号：US20150014419A1

公开(公告)日：2015-01-15

申请号：US14500343

申请日：2014-09-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Takaaki KOEN ,  Yuto YAKUBO ,  Makoto YANAGISAWA ,  Hisashi OHTANI ,  Eiji SUGIYAMA ,  Nozomi HORIKOSHI

IPC: G06K19/077

CPC classification number: G06K19/07735 ,  G06K19/07722 ,  G06K19/07794 ,  H01L23/295 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.

Abstract translation: 一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。 半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。 在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。 其中一个结构体设置在片上天线和增强天线之间。 在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω·cm 2 / cm 2的导电膜。

公开(公告)号：US20140332809A1

公开(公告)日：2014-11-13

申请号：US14445515

申请日：2014-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko SAITO ,  Kiyoshi KATO ,  Atsuo ISOBE

IPC: H01L27/06 ,  H01L29/786 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L27/0688 ,  G11C16/0433 ,  H01L21/02565 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78696

Abstract: With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.

Abstract translation: 通过包括氧化物半导体材料的晶体管和包括除了氧化物半导体之外的半导体材料的晶体管的组合，具有可以长时间保持数据并且对数字没有限制的新颖结构的半导体器件 的写作可以获得。 当用于将包括氧化物半导体的半导体材料的晶体管连接到包括氧化物半导体材料的晶体管的连接电极小于包含与连接电极连接的氧化物半导体以外的半导体材料的晶体管的电极时， 具有新颖结构的半导体器件可以高度集成，并且可以增加每单位面积的存储容量。

公开(公告)号：US20130335056A1

公开(公告)日：2013-12-19

申请号：US13908121

申请日：2013-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Koichiro KAMATA ,  Tsutomu MURAKAWA ,  Takahiro TSUJI ,  Kaori IKADA

IPC: G05F3/16

CPC classification number: G05F3/16 ,  G05F1/56 ,  G05F3/242

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract translation: 本发明的一个目的是提供一种具有改善的噪声容限的调节器电路。 在包括基于第一电源端子和第二电源端子之间的电位差产生参考电压的偏置电路的调节器电路中，以及基于参考电位向输出端子输出电位的电压调节器 在偏置电路的输入端，在电源端子与偏置电路中包含的晶体管的栅极连接的节点之间设置有旁路电容器。

公开(公告)号：US20130292671A1

公开(公告)日：2013-11-07

申请号：US13939223

申请日：2013-07-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/088

CPC classification number: H01L27/088 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1225

Abstract: It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

Abstract translation: 本发明的目的是提供具有新颖结构的半导体。 在半导体器件中，多个存储器元件串联连接，并且多个存储元件中的每一个包括第一至第三晶体管，从而形成存储器电路。 包括氧化物半导体层的第一晶体管的源极或漏极与第二和第三晶体管之一的栅极电接触。 含有氧化物半导体层的第一晶体管的极低的截止电流允许长时间地在第二和第三晶体管之一的栅电极中存储电荷，由此可以获得基本上永久的记忆效应。 不含氧化物半导体层的第二和第三晶体管在使用存储电路时允许高速操作。

公开(公告)号：US20250126843A1

公开(公告)日：2025-04-17

申请号：US18834020

申请日：2023-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10D30/67 ,  H01L23/528 ,  H10B12/00

Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. In each of the first to third transistors, the side surfaces of a metal oxide are covered with a source electrode and a drain electrode. The second and third transistors share the metal oxide. The capacitor is provided above the first to third transistors. A conductor including a region functioning as a write bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the first transistor. A conductor including a region functioning as a read bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the third transistor. The other of the source electrode and the drain electrode of the first transistor and a gate of the second transistor are electrically connected to one electrode of the capacitor.

公开(公告)号：US20250126777A1

公开(公告)日：2025-04-17

申请号：US18730461

申请日：2023-01-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10B12/00

Abstract: An electronic device including a first conductor, a second conductor, a first insulator, a second insulator, and a connection electrode is provided. The first insulator is provided over the first conductor and has a first opening overlapping with the first conductor. The second conductor is provided over the first insulator and has a second opening overlapping with the first conductor. The second insulator is provided over the second conductor and has a third opening overlapping with the first conductor. The second opening has a portion having a width smaller than a width of the third opening. The connection electrode is positioned inside the first opening, the second opening, and the third opening and is in contact with the top surface of the first conductor. The connection electrode includes a region in contact with part of the top surface and part of the side surface of the second conductor.