公开(公告)号：US09196626B2

公开(公告)日：2015-11-24

申请号：US14272853

申请日：2014-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/115 ,  H01L27/108 ,  G11C11/00 ,  H01L27/105 ,  H01L27/11

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

公开(公告)号：US09165632B2

公开(公告)日：2015-10-20

申请号：US14160800

申请日：2014-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Takuro Ohmaru ,  Yasuyuki Takahashi

IPC: G11C11/22 ,  G11C11/24

CPC classification number: G11C11/22 ,  G11C11/24

Abstract: Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor.

Abstract translation: 提供了具有降低的架空功率的存储器件。 一种存储装置，包括：第一电路，在供给电源电压的第一期间保持数据; 第二电路在第一时段中保存保留在第一电路中的数据，并且在不提供电源电压的第二周期内保留从第一电路保存的数据; 以及第三电路，在第二时段中保存保留在第二电路中的数据，并且在不提供电源电压的第三周期内保持从第二电路保存的数据。 第三电路包括其中沟道形成区域设置在氧化物半导体膜中的晶体管和通过晶体管提供对应于数据的电位的电容器。

公开(公告)号：US09153313B2

公开(公告)日：2015-10-06

申请号：US14223071

申请日：2014-03-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Takuro Ohmaru ,  Yasuyuki Takahashi

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/401 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C11/401 ,  G11C11/4074

Abstract: The first circuit has a function of retaining data in a first period during which a power supply voltage is supplied. The second circuit has functions of saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which application of the power supply voltage is stopped. The third circuit has functions of saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which application of the power supply voltage is stopped. The second circuit is capable of being written with the data for a shorter time than the third circuit. The third circuit is capable of maintaining the data for a longer time than the second circuit.

Abstract translation: 第一电路具有在提供电源电压的第一时段中保持数据的功能。 第二电路具有在第一时间段内保存保留在第一电路中的数据的功能，并且在停止施加电源电压的第二周期中保持从第一电路保存的数据。 第三电路具有在第二时段中保存保留在第二电路中的数据的功能，并且在停止施加电源电压的第三周期中保留从第二电路保存的数据。 第二电路能够以比第三电路更短的时间写入数据。 第三电路能够保持数据比第二电路更长的时间。

公开(公告)号：US09054201B2

公开(公告)日：2015-06-09

申请号：US13928425

申请日：2013-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  G11C16/04 ,  G11C16/26

CPC classification number: H01L27/1255 ,  G11C16/0433 ,  G11C16/26 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

Abstract translation: 本发明的目的是提供一种具有新颖结构的半导体器件，其中在数据存储时间中，即使在不提供电力的情况下也可以存储所存储的数据，并且对写入次数没有限制。 半导体器件包括：第一晶体管，包括第一源极和第一漏极; 使用氧化物半导体材料并且第一源电极和第一漏电极电连接的第一沟道形成区域; 在所述第一通道形成区域上的第一栅极绝缘层; 以及在所述第一栅极绝缘层上方的第一栅电极。 第一晶体管的第一源电极和第一漏电极之一和电容器的一个电极彼此电连接。

公开(公告)号：US20150084046A1

公开(公告)日：2015-03-26

申请号：US14492412

申请日：2014-09-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Hidekazu Miyairi ,  Shuhei Nagatsuka

IPC: H01L27/06 ,  H01L29/24

CPC classification number: H01L27/0629 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255

Abstract: A semiconductor device including a transistor and a capacitor which occupies a small area is provided. The semiconductor device includes a semiconductor, first and second conductive films each comprising a region in contact with top and side surfaces of the semiconductor, a first insulating film comprising a region in contact with the top and side surfaces of the semiconductor, a third conductive film comprising a region facing the top and side surfaces of the semiconductor with the first insulating film therebetween, a second insulating film which is in contact with the first conductive film and comprises an opening, a fourth conductive film comprising a region in contact with the opening, a third insulating film comprising a region facing the opening with the fourth conductive film therebetween, and a fifth conductive film comprising a region facing the fourth conductive film with the third insulating film therebetween.

Abstract translation: 提供了包括占据小面积的晶体管和电容器的半导体器件。 半导体器件包括半导体，第一和第二导电膜，每个包括与半导体的顶表面和侧表面接触的区域;第一绝缘膜，包括与半导体的顶表面和侧表面接触的区域;第三导电膜 包括面对半导体的顶表面和侧表面的区域，其间具有第一绝缘膜，与第一导电膜接触并包括开口的第二绝缘膜，包括与开口接触的区域的第四导电膜， 第三绝缘膜，其包括与其间具有第四导电膜的开口面对的区域;以及第五导电膜，其包括面对第四导电膜的区域，其间具有第三绝缘膜。

公开(公告)号：US20140339541A1

公开(公告)日：2014-11-20

申请号：US14272853

申请日：2014-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: H01L27/115 ,  H01L27/108

CPC classification number: H01L27/11563 ,  G11C11/005 ,  G11C11/412 ,  G11C14/0054 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10894 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

Abstract translation: 具有新型结构的半导体器件，其中提供了即使使用小型化元件来保持数据所需的存储容量。 在半导体器件中，电容器的电极是设置在与晶体管的栅极相同的层中的电极和设置在与晶体管的源极和漏极相同的层中的电极。 此外，在不同的层中设置提供晶体管的栅极的层和连接多个存储器中的晶体管的栅极的布线层。 利用这种结构，可以减小在晶体管的栅极周围形成的寄生电容，并且可以在更大的面积中形成电容器。

公开(公告)号：US20140326999A1

公开(公告)日：2014-11-06

申请号：US14336107

申请日：2014-07-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1052 ,  G11C11/405 ,  G11C16/0433 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7833 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract translation: 目的是提供具有新颖结构的半导体器件。 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管设置在包括半导体材料的衬底中。 第二晶体管包括氧化物半导体层。

公开(公告)号：US20140110704A1

公开(公告)日：2014-04-24

申请号：US14060447

申请日：2013-10-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/788

CPC classification number: H01L27/1225 ,  H01L27/1156 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78645 ,  H01L29/7869 ,  H01L29/788

Abstract: A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the oxide layer, a second drain electrode layer in contact with the oxide layer, a gate insulating film in contact with the oxide layer, a first gate electrode layer overlapping with the source electrode layer and the first drain electrode layer and overlapping with a top surface of the oxide layer with the gate insulating film interposed therebetween, a second gate electrode layer overlapping with the source electrode layer and the second drain electrode layer and overlapping with the top surface of the oxide layer with the gate insulating film interposed therebetween, and a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween.

Abstract translation: 半导体器件包括氧化物层，与氧化物层接触的源极电极层，与氧化物层接触的第一漏极电极层，与氧化物层接触的第二漏极电极层，与氧化物层接触的栅极绝缘膜 所述氧化物层与所述源极电极层和所述第一漏极电极层重叠并与所述氧化物层的顶表面重叠的第一栅极电极层与所述栅极绝缘膜插入其间，与所述源极电极层重叠的第二栅电极层 所述第二漏极电极层与所述氧化物层的顶面重叠，并且所述栅极绝缘膜与所述第二漏极电极层重叠，并且所述第三栅极电极层与所述氧化物层的侧面重叠，并且所述栅极绝缘膜插入其间。

公开(公告)号：US20140108836A1

公开(公告)日：2014-04-17

申请号：US14055200

申请日：2013-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Abstract translation: 提供以低功耗模式工作的微控制器。 微控制器包括CPU，存储器和诸如定时器电路的外围电路。 外围电路中的寄存器设置在与总线线路的接口中。 提供用于控制电源控制的电源门。 微控制器不仅可以在所有电路都有效的正常工作模式下工作，而且还可以在一些电路处于活动状态的低功耗模式下工作。 在诸如CPU的寄存器的寄存器中提供易失性存储器和非易失性存储器。 在电源停止之前，易失性存储器中的数据被备份在非易失性存储器中。 在操作模式返回到正常模式的情况下，当再次开始供电时，非易失性存储器中的数据被写回到易失性存储器中。

公开(公告)号：US20140092681A1

公开(公告)日：2014-04-03

申请号：US14068131

申请日：2013-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C11/40 ,  G11C2207/005 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/155 ,  H01L29/205

Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.

Abstract translation: 半导体器件包括：源极线; 有点线 字线 连接到位线和字线的存储单元; 驱动电路，其驱动多个第二信号线和多个字线，以选择由地址信号指定的存储单元; 产生写入电位和多个读取电位以供给写入电路和读取电路的电位产生电路; 以及控制电路，其基于将所述位线的电位与所述多个读取电位进行比较的所述读取电路的结果来选择用于校正的多个电压中的一个。