公开(公告)号：US10347621B2

公开(公告)日：2019-07-09

申请号：US15291564

申请日：2016-10-12

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US10186589B2

公开(公告)日：2019-01-22

申请号：US15865746

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/41 ,  H01L29/45 ,  H01L29/49 ,  H01L27/06 ,  H01L29/417 ,  H01L29/778

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US20180190778A1

公开(公告)日：2018-07-05

申请号：US15865746

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/778 ,  H01L27/06 ,  H01L29/417 ,  H01L29/20 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US10014231B1

公开(公告)日：2018-07-03

申请号：US15439191

申请日：2017-02-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L29/06 ,  H01L29/20 ,  G01R31/12 ,  H01L21/66 ,  H01L23/544 ,  H01L29/40 ,  H01L29/417 ,  H01L27/088 ,  G01R31/28

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US09985095B2

公开(公告)日：2018-05-29

申请号：US15182658

申请日：2016-06-15

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/324 ,  H01L21/225 ,  H01L21/761 ,  H01L21/266 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

公开(公告)号：US20180061932A1

公开(公告)日：2018-03-01

申请号：US15245511

申请日：2016-08-24

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Binghua Hu ,  Sameer Pendharkar

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/283 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L28/60 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/535

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

公开(公告)号：US20170301673A1

公开(公告)日：2017-10-19

申请号：US15636055

申请日：2017-06-28

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US09735265B2

公开(公告)日：2017-08-15

申请号：US15348725

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/762 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

公开(公告)号：US20170148905A1

公开(公告)日：2017-05-25

申请号：US14951927

申请日：2015-11-25

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L21/7605 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.

公开(公告)号：US09543944B2

公开(公告)日：2017-01-10

申请号：US15168458

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H03K17/687 ,  H01L29/20 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L27/092 ,  H03F3/193 ,  H03F3/195 ,  H02M5/257

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。