公开(公告)号：US20220230910A1

公开(公告)日：2022-07-21

申请号：US17715261

申请日：2022-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US11302567B2

公开(公告)日：2022-04-12

申请号：US16917159

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US20220059405A1

公开(公告)日：2022-02-24

申请号：US17001247

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/66 ,  H01L23/535 ,  H01L23/532

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

公开(公告)号：US20220037465A1

公开(公告)日：2022-02-03

申请号：US17119102

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

公开(公告)号：US20210367038A1

公开(公告)日：2021-11-25

申请号：US17394399

申请日：2021-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225

Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm−3 and about 1020 cm−3.

公开(公告)号：US20210272816A1

公开(公告)日：2021-09-02

申请号：US16951955

申请日：2020-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Ya-Lun Chen ,  Tsai-Yu Huang ,  Yahru Cheng ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  G03F7/16

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

公开(公告)号：US20210202255A1

公开(公告)日：2021-07-01

申请号：US17201073

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US20210098365A1

公开(公告)日：2021-04-01

申请号：US16805834

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC: H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US10566242B2

公开(公告)日：2020-02-18

申请号：US15376719

申请日：2016-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Tsan-Chun Wang ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L21/8234 ,  H01L21/223 ,  H01L29/66

Abstract: A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.

公开(公告)号：US20200013623A1

公开(公告)日：2020-01-09

申请号：US16568585

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3105

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.